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1. 发明授权

US06509219B2 Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch 失效
公开(公告)号：US06509219B2
公开(公告)日：2003-01-21
申请号：US09928212
申请日：2001-08-10
申请人： Len Y. Tsou , Hongwen Yan , Qingyun Yang , Chienfan Yu
发明人： Len Y. Tsou , Hongwen Yan , Qingyun Yang , Chienfan Yu
IPC分类号： H01L21336
CPC分类号： H01L21/28114 , H01L29/42376
摘要： A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

2. 发明授权

US06864041B2 Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching 失效
标题翻译：使用等离子体蚀刻的100nm以下器件的栅极线宽定制和临界尺寸控制
公开(公告)号：US06864041B2
公开(公告)日：2005-03-08
申请号：US09847479
申请日：2001-05-02
申请人： Jeffrey J. Brown , Sadanand Vinayak Deshpande , David V. Horak , Maheswaran Surendra , Len Y. Tsou , Qingyun Yang , Chienfan Yu , Ying Zhang
发明人： Jeffrey J. Brown , Sadanand Vinayak Deshpande , David V. Horak , Maheswaran Surendra , Len Y. Tsou , Qingyun Yang , Chienfan Yu , Ying Zhang
IPC分类号： G03F7/40 , G03F7/42 , H01L21/033 , G03F7/36 , H01L21/461
CPC分类号： G03F7/40 , G03F7/427 , H01L21/0337 , H01L21/0338
摘要： A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.
摘要翻译：一种在晶片上制造电子芯片的方法，其中在晶片上形成以预定的较低分辨率的第一掩模，然后在第一组条件下在预定时间段内蚀刻以实现低于电流分辨率极限的掩模平版印刷然后将蚀刻的掩模用作用于在下层上蚀刻材料的硬掩模。

3. 发明授权

US06541320B2 Method to controllably form notched polysilicon gate structures 失效
标题翻译：可控地形成切口多晶硅栅极结构的方法
公开(公告)号：US06541320B2
公开(公告)日：2003-04-01
申请号：US09928210
申请日：2001-08-10
申请人： Jeffrey Brown , Richard Wise , Hongwen Yan , Qingyun Yang , Chienfan Yu
发明人： Jeffrey Brown , Richard Wise , Hongwen Yan , Qingyun Yang , Chienfan Yu
IPC分类号： H01L21336
CPC分类号： H01L21/32137 , H01L21/28114 , H01L21/32139 , H01L21/82385 , H01L29/42376
摘要： A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof.
摘要翻译：一种用于形成在栅极介电层上具有栅极导体层的缺口栅极结构的方法和结构。栅极导体层具有第一厚度。本发明的方法包括在栅极导体层上图案化掩模，在未被掩模保护的区域中将栅极导体层蚀刻到减小的厚度（减小的厚度小于第一厚度），在栅极导体上沉积钝化膜蚀刻钝化膜以从栅极导体层的水平部分去除钝化膜（使用各向异性蚀刻），选择性地蚀刻栅极导体层以从不受掩模或钝化膜保护的所有区域去除栅极导体层。这在栅极导体与栅极介电层相遇的拐角处形成栅极导体层内的底切凹口。钝化膜包括含C的膜，含Si膜，含Si-C的膜或其组合。

4. 发明授权

US06960510B2 Method of making sub-lithographic features 失效
标题翻译：制作亚光刻特征的方法
公开(公告)号：US06960510B2
公开(公告)日：2005-11-01
申请号：US10187579
申请日：2002-07-01
申请人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
发明人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L21/033 , H01L21/265 , H01L21/28 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/8236
CPC分类号： H01L21/26586 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L21/3086 , H01L21/3088 , H01L21/31144
摘要： A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.
摘要翻译：提供了形成具有亚光刻尺寸的结构的方法。该方法包括：在基底上形成倒角心轴，心轴具有成角度的表面; 以及执行成角度的离子注入以在所述衬底中获得注入的阴影区域，所述植入的荫罩具有至少一个亚光刻尺寸。

5. 发明授权

US06828187B1 Method for uniform reactive ion etching of dual pre-doped polysilicon regions 失效
标题翻译：双预掺杂多晶硅区域的均匀反应离子蚀刻方法
公开(公告)号：US06828187B1
公开(公告)日：2004-12-07
申请号：US10707709
申请日：2004-01-06
申请人： Joyce C. Liu , Len Y. Tsou , Qingyun Yang
发明人： Joyce C. Liu , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32137
摘要： A method for forming a semiconductor device, includes forming a first locally doped semiconductor region of a first conductivity type and a second locally doped semiconductor region of a second conductivity type over an undoped, lower semiconductor region. A first etch is implemented to simultaneously create a desired pattern in the first and second locally doped semiconductor regions in a manner that also provides a first passivation of exposed sidewalls thereof, wherein the first etch removes material from the first and second locally doped regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the desired pattern in the undoped, lower semiconductor region in a manner that protects the first and second locally doped regions from additional material removal therefrom.
摘要翻译：一种用于形成半导体器件的方法，包括在未掺杂的下半导体区域上形成第一导电类型的第一局部掺杂半导体区域和第二导电类型的第二局部掺杂半导体区域。实施第一蚀刻以在第一和第二局部掺杂的半导体区域中以提供其暴露的侧壁的第一钝化的方式同时产生期望的图案，其中第一蚀刻从第一和第二局部掺杂区域中去除材料相对于基本上恒定的速率，并且以基本上各向异性的方式。实现第二蚀刻以在未掺杂的较低半导体区域中以保护第一和第二局部掺杂区域免除额外材料的方式完成所需图案。

6. 发明授权

US06703269B2 Method to form gate conductor structures of dual doped polysilicon 有权
标题翻译：形成双掺杂多晶硅栅极导体结构的方法
公开(公告)号：US06703269B2
公开(公告)日：2004-03-09
申请号：US10114829
申请日：2002-04-02
申请人： Jeffrey J. Brown , Len Y. Tsou , Qingyun Yang
发明人： Jeffrey J. Brown , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： A method for manufacturing a semiconductor chip which has transistors is disclosed. The transistors include first type transistors which have a first type of doping and second type transistors which have a second type of doping different than the first type of doping. The method includes forming a conductive layer on a substrate. The conductive layer includes first regions that have the first type of doping and second regions have the second type of doping. The invention patterns a mask over the conductive layer, and the mask protects portions of the conductive layer where gate conductors will be located. Next, the invention partially etches unprotected portions of the conductive layer. The partially etching process allows a layer of the unprotected portions to remain, such that the substrate is not exposed by the partially etching process. The invention forms a passivating layer on exposed vertical surfaces of the conductive layer and completely etches unprotected portions of the conductive layer to expose the substrate. The invention then dopes exposed portions of the substrate to form source/drain regions.
摘要翻译：公开了一种制造具有晶体管的半导体芯片的方法。晶体管包括具有第一类型掺杂的第一类型晶体管和具有不同于第一类型掺杂的第二类型掺杂的第二类型晶体管。该方法包括在衬底上形成导电层。导电层包括具有第一类型的掺杂的第一区域和第二区域具有第二类型的掺杂。本发明在导电层上形成掩模，并且掩模保护导电层在栅极导体将被定位的部分。接下来，本发明部分地蚀刻导电层的未受保护的部分。部分蚀刻工艺允许保留未保护部分的层，使得基板不被部分蚀刻工艺暴露。本发明在导电层的暴露的垂直表面上形成钝化层，并且完全蚀刻导电层的未受保护的部分以暴露衬底。然后，本发明掺杂衬底的暴露部分以形成源极/漏极区域。

7. 发明申请

US20080182372A1 METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS 审中-公开
标题翻译：形成改善间隔物的方法，用于改善耐压氮化膜的有效性
公开(公告)号：US20080182372A1
公开(公告)日：2008-07-31
申请号：US11669645
申请日：2007-01-31
申请人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/6653 , H01L21/3146 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate insulating layer, and substrate; etching the first carbon-based layer so as to create a first set of carbon spacers; forming a second carbon-based layer over the gate conductor, gate insulating layer, substrate, and first set of carbon spacers; etching the second carbon-based layer so as to create a second set of carbon spacers; forming silicide contacts on the gate conductor, and on source and drain regions formed in the substrate; removing the first and second sets of carbon spacers; and forming a stress-inducing nitride layer over the substrate, silicide contacts, gate conductor, and gate insulating layer.
摘要翻译：形成互补金属氧化物半导体（CMOS）器件的方法包括在图案化栅极导体的侧壁和顶表面上以及形成在半导体衬底上的栅极绝缘层的侧壁上形成氧化物层; 在栅极导体，栅极绝缘层和衬底上形成第一碳基层; 蚀刻第一碳基层以产生第一组碳间隔物; 在栅极导体，栅极绝缘层，衬底和第一组碳隔离物上形成第二碳基层; 蚀刻第二碳基层以产生第二组碳间隔物; 在栅极导体上形成硅化物触点，以及在衬底中形成的源极和漏极区上; 去除第一和第二组碳间隔物; 以及在衬底上形成应力诱导氮化物层，硅化物接触，栅极导体和栅极绝缘层。

8. 发明申请

US20120256278A1 Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure 有权
标题翻译：去除栅极结构侧壁上高K电介质层的方法
公开(公告)号：US20120256278A1
公开(公告)日：2012-10-11
申请号：US13080084
申请日：2011-04-05
申请人： Ying Zhang , Qingyun Yang , Hongwen Yan
发明人： Ying Zhang , Qingyun Yang , Hongwen Yan
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/26586 , H01L21/823462 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.
摘要翻译：一种半导体结构，以及形成半导体结构的方法，其包括半导体衬底上的栅极结构，其中栅极结构包括栅极导体和高k栅极电介质层。高k栅极电介质层与栅极导体的基极接触并且存在于栅极导体的侧壁上，尺寸小于栅极结构的高度的1/4。半导体结构还包括在栅极结构的相对侧上存在于半导体衬底中的源极区和漏极区。

9. 发明申请

US20080242070A1 INTEGRATION SCHEMES FOR FABRICATING POLYSILICON GATE MOSFET AND HIGH-K DIELECTRIC METAL GATE MOSFET 有权
标题翻译：用于制造多晶硅栅极MOSFET和高K介电金属栅极MOSFET的集成方案
公开(公告)号：US20080242070A1
公开(公告)日：2008-10-02
申请号：US11694104
申请日：2007-03-30
申请人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28194 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.
摘要翻译：公开了用于制造双栅极半导体结构的多重集成方案。通过采用新颖的集成方案，尽管栅极堆叠的组成差异以及蚀刻速率的差异，但是在同一半导体衬底上形成多晶硅栅极MOSFET和高k介质金属栅极MOSFET。对于一种类型的栅电极使用薄多晶硅层，并且在这些集成方案中使用含硅层用于其他类型的栅电极，以平衡不同的蚀刻速率并且能够蚀刻两个不同的栅极堆叠。

10. 发明授权

US08481389B2 Method of removing high-K dielectric layer on sidewalls of gate structure 有权
标题翻译：去除栅极结构侧壁上的高K电介质层的方法
公开(公告)号：US08481389B2
公开(公告)日：2013-07-09
申请号：US13080084
申请日：2011-04-05
申请人： Ying Zhang , Qingyun Yang , Hongwen Yan
发明人： Ying Zhang , Qingyun Yang , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26586 , H01L21/823462 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.
摘要翻译：一种半导体结构，以及形成半导体结构的方法，其包括半导体衬底上的栅极结构，其中栅极结构包括栅极导体和高k栅极电介质层。高k栅极电介质层与栅极导体的基极接触并且存在于栅极导体的侧壁上，尺寸小于栅极结构的高度的1/4。半导体结构还包括在栅极结构的相对侧上存在于半导体衬底中的源极区和漏极区。

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