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1. 发明授权

US06459049B1 High density signal routing 有权
标题翻译：高密度信号路由
公开(公告)号：US06459049B1
公开(公告)日：2002-10-01
申请号：US09885299
申请日：2001-06-20
申请人： Leah M. Miller , Farshad Ghahghahi , Edwin M. Fulcher , Aritharan Thurairajaratnam
发明人： Leah M. Miller , Farshad Ghahghahi , Edwin M. Fulcher , Aritharan Thurairajaratnam
IPC分类号： H01R909
CPC分类号： H05K1/0216 , H01R31/06 , H05K1/112 , H05K1/117 , H05K2201/09236 , H05K2201/09281 , H05K2201/09727
摘要： A structure for receiving electrical signals near a central portion of the structure and distributing the electrical signals to a peripheral portion of the structure. The structure has a first set of contacts arranged in an array near the central portion of the structure. Electrically conductive traces connect the first set of contacts to a second set of contacts, where each of the electrically conductive traces has at least a first segment, a second segment, and a third segment. The first segment of each of the electrically conductive traces has relatively narrow width and spacing. The first segment of each of the electrically conductive traces is connected on a first end of the first segment to one of the first set of contacts and on a second end of the first segment to the second segment of each of the electrically conductive traces. The second segment of each of the electrically conductive traces has relatively intermediate width and spacing. The second segment of each of the electrically conductive traces is connected on a first end of the second segment to the second end of the first segment and on a second end of the second segment to the third segment of each of the electrically conductive traces. The third segment of each of the electrically conductive traces has relatively wide width and spacing. The third segment of each of the electrically conductive traces is connected on a first end of the third segment to the second end of the second segment and on a second end of the third segment to one of the second set of contacts.
摘要翻译：一种用于在所述结构的中心部分附近接收电信号并将所述电信号分配到所述结构的外围部分的结构。该结构具有靠近结构的中心部分排列成阵列的第一组触点。导电迹线将第一组触点连接到第二组触点，其中每个导电迹线具有至少第一段，第二段和第三段。每个导电迹线的第一段具有相对较窄的宽度和间隔。每个导电迹线的第一段在第一段的第一端连接到第一组触点中的一个，并且在第一段的第二端连接到每个导电迹线的第二段。每个导电迹线的第二段具有相对中间的宽度和间隔。每个导电迹线的第二段在第二段的第一端连接到第一段的第二端，并且在第二段的第二端连接到每个导电迹线的第三段。每个导电迹线的第三段具有相对宽的宽度和间隔。每个导电迹线的第三段在第三段的第一端连接到第二段的第二端，并且在第三段的第二端连接到第二组接触中的一个。

2. 发明授权

US06744130B1 Isolated stripline structure 有权
标题翻译：隔离带状线结构
公开(公告)号：US06744130B1
公开(公告)日：2004-06-01
申请号：US10615063
申请日：2003-07-08
申请人： Leah M. Miller , Aritharan Thurairajaratnam , Edwin M. Fulcher
发明人： Leah M. Miller , Aritharan Thurairajaratnam , Edwin M. Fulcher
IPC分类号： H01L2348
CPC分类号： H05K1/0245 , H01L23/66 , H01L2223/6616 , H01L2224/16 , H01L2924/15173 , H01L2924/15311 , H01L2924/3011 , H05K3/4602 , H05K2201/09236 , H05K2201/093 , H05K2201/09327 , H05K2201/09627 , H05K2201/09663
摘要： A package substrate having separate routing layers for transmitter signals and receiver signals, which signals are routed in differential pairs. The differential pairs of signal routing lines are isolated between a separate ground plane for transmitter and receiver traces and dedicated power planes, where a single power plane is dedicated to a single differential pair of signal routing lines. In this manner, a high degree of electrical isolation exists not only between the transmitter signal traces and the receiver signal traces, which are on different layers, but also between different differential pairs of signal routing lines on the same layer, each of which has its own dedicated power plane. Thus, a very high speed core routing system can be designed in a package substrate that can then be adapted as necessary to support a broad range of different integrated circuit designs.
摘要翻译：封装衬底具有用于发射机信号和接收机信号的分离的路由层，哪些信号以差分对路由。信号路由线路的差分对在用于发射器和接收器迹线的独立接地平面和专用功率平面之间隔离，其中单个功率平面专用于单个差分信号路由线路对。以这种方式，高度的电隔离不仅存在于发射机信号迹线和位于不同层上的接收机信号迹线之间，而且存在于同一层上的信号路由线路的不同差分对之间，自有专用电源机。因此，可以在封装衬底中设计非常高速的芯路由系统，然后可以根据需要进行调整，以支持各种不同的集成电路设计。

3. 发明授权

US06791177B1 Integrated circuit packaging that uses guard conductors to isolate noise-sensitive signals within the package substrate 有权
标题翻译：集成电路封装，其使用保护导体来隔离封装衬底内的噪声敏感信号
公开(公告)号：US06791177B1
公开(公告)日：2004-09-14
申请号：US10435805
申请日：2003-05-12
申请人： Leah M. Miller , Aritharan Thurairajaratnam , Edwin M. Fulcher
发明人： Leah M. Miller , Aritharan Thurairajaratnam , Edwin M. Fulcher
IPC分类号： H01L2352
CPC分类号： H05K1/0219 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K2201/09236 , H05K2201/09618 , H01L2924/00
摘要： A package substrate is contemplated herein for reducing cross-talk for noise-sensitive signals. The package substrate includes noise-sensitive conductors adapted to receive the noise-sensitive signals. In one embodiment, the cross-sectional width of the noise-sensitive conductors is increased to reduce certain parasitic effects such as resistance and/or inductance. The package substrate also includes guard conductors which are arranged co-planar with and substantially parallel to the noise-sensitive conductors. A plurality of vias spaced equidistant from one another extends from a ground conductor to the guard conductors, providing a substantially uniform voltage across the guard conductors. The overall effect will reduce the inductive and capacitive cross-talk from neighboring signals and increase the signal integrity of noise-sensitive signals.
摘要翻译：本文考虑的封装衬底用于减少噪声敏感信号的串扰。封装衬底包括适于接收噪声敏感信号的噪声敏感导体。在一个实施例中，噪声敏感导体的横截面宽度增加以减少某些寄生效应，例如电阻和/或电感。封装衬底还包括与噪声敏感导体共面并基本上平行的保护导体。彼此间隔开等距的多个通孔从接地导体延伸到保护导体，从而在保护导体上提供基本均匀的电压。整体效果将减少相邻信号的电感和电容串扰，并增加噪声敏感信号的信号完整性。

4. 发明授权

US06534968B1 Integrated circuit test vehicle 失效
标题翻译：集成电路测试车
公开(公告)号：US06534968B1
公开(公告)日：2003-03-18
申请号：US09928071
申请日：2001-08-10
申请人： Leah M. Miller , Anand Govind , Zafer Kutlu , Chao-Wen Chung , Aritharan Thurairajaratnam
发明人： Leah M. Miller , Anand Govind , Zafer Kutlu , Chao-Wen Chung , Aritharan Thurairajaratnam
IPC分类号： G01R3100
CPC分类号： G01R31/04 , G01R31/2853 , G01R31/31716 , H05K1/0268 , H05K3/3436
摘要： An apparatus for detecting failures in electrical connections between an integrated circuit package substrate and a circuit board. The substrate has substrate electrical contacts that are electrically connected one to another in first sets in a first region of the substrate. The circuit board has circuit board electrical contacts that are electrically connected one to another in second sets in a second region of the circuit board. The substrate electrical contacts align with and make electrical contact with the circuit board electrical contacts. The first region of the substrate aligns with the second region of the circuit board when the substrate electrical contacts make electrical contact with the circuit board electrical contacts. The first sets of substrate electrical contacts form chains of electrical contacts with the second sets of circuit board electrical contacts. The chains of electrical contacts loop back and forth electrically between the substrate and the circuit board.
摘要翻译：一种用于检测集成电路封装衬底和电路板之间的电连接故障的装置。衬底具有在衬底的第一区域中的第一组中彼此电连接的衬底电触点。电路板具有在电路板的第二区域中在第二组中彼此电连接的电路板电触点。基板电触点与电路板电触点对齐并与之电接触。当基板电触头与电路板电触点电接触时，基板的第一区域与电路板的第二区域对齐。第一组基板电触点与第二组电路板电触点形成电触点链。电触头链在基板和电路板之间电连接。

5. 发明授权

US07319272B2 Ball assignment system 有权
标题翻译：球分配系统
公开(公告)号：US07319272B2
公开(公告)日：2008-01-15
申请号：US11097895
申请日：2005-04-01
申请人： Arun Ramakrishnan , Farshad Ghahghahi , Aritharan Thurairajaratnam , Leah M. Miller
发明人： Arun Ramakrishnan , Farshad Ghahghahi , Aritharan Thurairajaratnam , Leah M. Miller
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/34
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01L2924/15311 , H05K1/112 , H05K2201/09227 , H05K2201/09236 , H05K2201/10734 , H01L2924/00
摘要： A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern. Substantially all of the contacts are disposed at a standard pitch one from another on a single contact surface.
摘要翻译：包括设置在图案的第一部分中的高速发射器触点的接触图案，其中高速发射器接触设置在发射机差分对中。高速接收器触点设置在图案的第二部分中，其中图案的第一部分不与图案的第二部分分散，并且高速接收器触点设置在接收器差分对中。在图案的第一部分和图案的第二部分之间设置至少一条其他触点的一条直线，其他触点不包含任何高速发送器触点和高速接收器触点。低速IO触点设置在图案的第三部分中，其中图案的第三部分相对于图案的第一部分和图案的第二部分布置在图案的内部。基本上所有的触点在单个接触表面上彼此之间以标准间距设置。

6. 发明授权

US06963129B1 Multi-chip package having a contiguous heat spreader assembly 有权
标题翻译：具有连续散热器组件的多芯片封装
公开(公告)号：US06963129B1
公开(公告)日：2005-11-08
申请号：US10464178
申请日：2003-06-18
申请人： Thomas Evans , Stan Mihelcic , Leah M. Miller , Kumar Nagarajan , Edwin M. Fulcher
发明人： Thomas Evans , Stan Mihelcic , Leah M. Miller , Kumar Nagarajan , Edwin M. Fulcher
IPC分类号： H01L23/10 , H01L23/34 , H01L23/36 , H01L25/065
CPC分类号： H01L23/36 , H01L25/0655 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16195 , H01L2924/19105
摘要： A system and method are provided for forming a multi-chip package. The multi-chip package includes a multi-layer substrate and a heat spreader of single, unibody construction. At least two integrated circuits are coupled between the multi-layer substrate and the heat spreader. The integrated circuits are spaced from one another to allow airflow between those circuits and a portion of the underside surface of the heat spreader. Depending on the layout of the package, a passive device can also be placed in the space between integrated circuits. The passive device extends upward a spaced distance from the underneath surface of the heat spreader so as not to block the airflow therebetween. The multi-chip package can accommodate integrated circuits that are either all packaged, all unpackaged, or a combination of each. If packaged and unpackaged integrated circuits are placed on the multi-layer substrate, the heat spreader can extend in two separate planes to accommodate the different thicknesses of those packaged and unpackaged integrated circuits. Alternatively, a second heat spreader can be placed on a relatively thin integrated circuit so that the upper surface of the second heat spreader is coplanar with an upper surface of a relatively thick integrated circuit. This will allow a planar heat spreader to be arranged across the thick integrated circuit and the second heat spreader. In all instances, however, the heat spreader extends as a single, contiguous unibody element across the entire multi-chip package.
摘要翻译：提供了一种用于形成多芯片封装的系统和方法。多芯片封装包括多层基板和单一单体结构的散热器。至少两个集成电路耦合在多层基板和散热器之间。集成电路彼此间隔开，以允许这些电路之间的气流和散热器的下表面的一部分。根据封装的布局，无源器件也可放置在集成电路之间的空间中。被动装置从散热器的下表面向上延伸一定距离，以便不阻挡散热器之间的气流。多芯片封装可以容纳所有封装，所有未封装的封装或各自的组合的集成电路。如果封装和未封装的集成电路放置在多层基板上，散热器可以在两个独立的平面中延伸，以适应那些封装和未封装的集成电路的不同厚度。或者，可以将第二散热器放置在相对薄的集成电路上，使得第二散热器的上表面与相对较厚的集成电路的上表面共面。这将允许平面散热器布置在厚集成电路和第二散热器之间。然而，在所有情况下，散热器在整个多芯片封装上延伸为单个，连续的一体元件。

7. 发明授权

US06762366B1 Ball assignment for ball grid array package 有权
标题翻译：球栅阵列包的球分配
公开(公告)号：US06762366B1
公开(公告)日：2004-07-13
申请号：US09844530
申请日：2001-04-27
申请人： Leah M. Miller , Farshad Ghahghahi , Edwin M. Fulcher
发明人： Leah M. Miller , Farshad Ghahghahi , Edwin M. Fulcher
IPC分类号： H05K100
CPC分类号： H01L23/49838 , H01L23/50 , H01L2924/0002 , H01L2924/15173 , H05K1/112 , H05K2201/09227 , H05K2201/10734 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A printed circuit board having contacts in a contact array of rows and columns. Groups of n columns of the contacts are electrically connected to n−1 columns of vias disposed interstitially in a via array between the n columns of the contacts. A major vertical routing channel is formed between adjacent groups of n columns of the contacts and the n−1 columns of vias. First electrical traces are electrically connected to a first number of the vias. The first electrical traces are routed to an outside edge of the via array through the major vertical routing channel.
摘要翻译：具有行和列的接触阵列中的触点的印刷电路板。触点的n列的组电连接到间隙地布置在接触件的n列之间的通孔阵列中的n-1列通孔。主要的垂直布线通道形成在相邻的n列的触点组和n-1列的通孔之间。第一电迹线与第一数目的通孔电连接。第一电迹线通过主垂直路由通道路由到通孔阵列的外边缘。

8. 发明授权

US06768386B1 Dual clock package option 有权
标题翻译：双时钟包选项
公开(公告)号：US06768386B1
公开(公告)日：2004-07-27
申请号：US10420219
申请日：2003-04-22
申请人： Leah M. Miller
发明人： Leah M. Miller
IPC分类号： H03H700
CPC分类号： H01L23/49838 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H01L2924/16152 , H01L2224/0401
摘要： A package substrate having a first layer adapted to received an integrated circuit, with electrically conductive contacts adapted to send and receive signals to and from the integrated circuit. The first layer includes a ground plane. A second layer is disposed underneath the first layer, and has electrically conductive traces, including a single ended clock signal trace and a set of two differential clock signal traces. The single ended clock signal trace and the set of two differential clock signal traces are substantially surrounded by grounded guard traces from all other electrically conductive traces on the second layer. A first electrically nonconductive layer is disposed between the first layer and the second layer.
摘要翻译：一种封装衬底，具有适于接收集成电路的第一层，其中导电触点适于向集成电路发送信号和从集成电路接收信号。第一层包括接地层。第二层设置在第一层下方，并且具有导电迹线，包括单端时钟信号迹线和一组两个差分时钟信号迹线。单端时钟信号迹线和两个差分时钟信号迹线的集合基本上被来自第二层上所有其它导电迹线的接地保护迹线包围。第一非导电层设置在第一层和第二层之间。

9. 发明授权

US07414322B2 High speed interface design 有权
标题翻译：高速接口设计
公开(公告)号：US07414322B2
公开(公告)日：2008-08-19
申请号：US11193808
申请日：2005-07-29
申请人： Leah M. Miller , Gregory S. Winn
发明人： Leah M. Miller , Gregory S. Winn
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L23/49822 , H01L23/50 , H01L23/66 , H01L2223/6638 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2924/15173 , H01L2924/3011 , H05K1/0219 , H05K1/0245 , H05K1/112 , H05K2201/09236 , H05K2201/09627 , H05K2201/0979 , H05K2201/10674
摘要： The embodiments of the present invention are directed toward the design of routing patterns, including elements such as contacts, traces, and vias, for high speed differential signal pairs in integrated circuit package substrates.
摘要翻译：本发明的实施例涉及布线图案的设计，包括用于集成电路封装基板中的高速差分信号对的诸如触点，迹线和通孔的元件。

10. 发明授权

US06445066B1 Splitting and assigning power planes 有权
标题翻译：拆分和分配电源平面
公开(公告)号：US06445066B1
公开(公告)日：2002-09-03
申请号：US09885491
申请日：2001-06-20
申请人： Leah M. Miller
发明人： Leah M. Miller
IPC分类号： H01L2352
CPC分类号： H01L23/50 , H01L23/49838 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method for assigning signal traces to one of a plurality of power planes on a power layer of an integrated circuit package. The integrated circuit package has an integrated circuit signal contact region, a top routing layer, and a bottom routing layer. The power layer underlies both the top routing layer and the bottom routing layer. First signal traces on the bottom routing layer are routed from contacts disposed in a core portion of the integrated circuit signal contact region to first ball contacts disposed within a first perimeter of the integrated circuit package. The first perimeter has dimension corresponding to a first distance from the integrated circuit signal contact region. Second signal traces on the top routing layer are routed from contacts disposed in a peripheral portion of the integrated circuit signal contact region to second ball contacts. The second ball contacts are disposed outside of the first perimeter of the integrated circuit package and within a second perimeter of the integrated circuit package. The second perimeter has dimensions corresponding to a second distance from the integrated circuit signal contact region, where the second distance is greater than the first distance. The power layer is segmented into the plurality of power planes. At least a first power plane of the plurality of power planes is bounded within the first perimeter. The first power plane is configured to carry a first voltage corresponding to the first signal traces. The first ball contacts are in proximity to the first power plane. At least a second power plane of the plurality of power planes is bounded between the first perimeter and the second perimeter. The second power plan is configured to carry a second voltage corresponding to the second signal traces. The second ball contacts are in proximity to the second power plane.
摘要翻译：一种用于将信号迹线分配给集成电路封装的功率层上的多个功率层之一的方法。集成电路封装具有集成电路信号接触区域，顶部路由层和底部路由层。功率层位于顶层路由层和底层路由层之下。底部布线层上的第一信号迹线从布置在集成电路信号接触区域的核心部分中的触点传送到布置在集成电路封装的第一周边内的第一球触点。第一周边具有对应于与集成电路信号接触区域的第一距离的尺寸。顶部布线层上的第二信号迹线从布置在集成电路信号接触区域的外围部分的触点路由到第二球触点。第二球接触件设置在集成电路封装的第一周边的外侧并且在集成电路封装的第二周边内。第二周边具有对应于距集成电路信号接触区域的第二距离的尺寸，其中第二距离大于第一距离。功率层被分割成多个电源层。多个电力平面中的至少第一电力平面在第一周边内是有界的。第一电源平面被配置为承载对应于第一信号迹线的第一电压。第一个球触点靠近第一个动力平面。多个电力平面中的至少第二电力平面被界定在第一周界和第二周边之间。第二电源方案被配置为承载对应于第二信号迹线的第二电压。第二个球触点靠近第二个电源平面。

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