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1. 发明授权

US06963129B1 Multi-chip package having a contiguous heat spreader assembly 有权
标题翻译：具有连续散热器组件的多芯片封装
公开(公告)号：US06963129B1
公开(公告)日：2005-11-08
申请号：US10464178
申请日：2003-06-18
申请人： Thomas Evans , Stan Mihelcic , Leah M. Miller , Kumar Nagarajan , Edwin M. Fulcher
发明人： Thomas Evans , Stan Mihelcic , Leah M. Miller , Kumar Nagarajan , Edwin M. Fulcher
IPC分类号： H01L23/10 , H01L23/34 , H01L23/36 , H01L25/065
CPC分类号： H01L23/36 , H01L25/0655 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16195 , H01L2924/19105
摘要： A system and method are provided for forming a multi-chip package. The multi-chip package includes a multi-layer substrate and a heat spreader of single, unibody construction. At least two integrated circuits are coupled between the multi-layer substrate and the heat spreader. The integrated circuits are spaced from one another to allow airflow between those circuits and a portion of the underside surface of the heat spreader. Depending on the layout of the package, a passive device can also be placed in the space between integrated circuits. The passive device extends upward a spaced distance from the underneath surface of the heat spreader so as not to block the airflow therebetween. The multi-chip package can accommodate integrated circuits that are either all packaged, all unpackaged, or a combination of each. If packaged and unpackaged integrated circuits are placed on the multi-layer substrate, the heat spreader can extend in two separate planes to accommodate the different thicknesses of those packaged and unpackaged integrated circuits. Alternatively, a second heat spreader can be placed on a relatively thin integrated circuit so that the upper surface of the second heat spreader is coplanar with an upper surface of a relatively thick integrated circuit. This will allow a planar heat spreader to be arranged across the thick integrated circuit and the second heat spreader. In all instances, however, the heat spreader extends as a single, contiguous unibody element across the entire multi-chip package.
摘要翻译：提供了一种用于形成多芯片封装的系统和方法。多芯片封装包括多层基板和单一单体结构的散热器。至少两个集成电路耦合在多层基板和散热器之间。集成电路彼此间隔开，以允许这些电路之间的气流和散热器的下表面的一部分。根据封装的布局，无源器件也可放置在集成电路之间的空间中。被动装置从散热器的下表面向上延伸一定距离，以便不阻挡散热器之间的气流。多芯片封装可以容纳所有封装，所有未封装的封装或各自的组合的集成电路。如果封装和未封装的集成电路放置在多层基板上，散热器可以在两个独立的平面中延伸，以适应那些封装和未封装的集成电路的不同厚度。或者，可以将第二散热器放置在相对薄的集成电路上，使得第二散热器的上表面与相对较厚的集成电路的上表面共面。这将允许平面散热器布置在厚集成电路和第二散热器之间。然而，在所有情况下，散热器在整个多芯片封装上延伸为单个，连续的一体元件。

2. 发明授权

US07117467B2 Methods for optimizing package and silicon co-design of integrated circuit 有权
标题翻译：优化集成电路封装和硅协同设计的方法
公开(公告)号：US07117467B2
公开(公告)日：2006-10-03
申请号：US10918933
申请日：2004-08-16
申请人： Anwar Ali , Stan Mihelcic , James G. Monthie
发明人： Anwar Ali , Stan Mihelcic , James G. Monthie
IPC分类号： G06F17/50 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/488
CPC分类号： G06F17/5068
摘要： The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.
摘要翻译：本发明涉及用于优化集成电路的封装和硅协同设计的方法。基于包括至少一个凸块图案模板的第一库创建用于集成电路的复合凸块图案。然后审查集成电路的PCB和晶片约束。基于包括至少一个部分封装模板的第二库生成集成电路的部分封装设计。开始用于所述集成电路的部分硅设计。然后完成集成电路的完整封装设计。集成电路的全硅设计完成。

3. 发明申请

US20070188188A1 Structured Integrated Circuit Device 有权
标题翻译：结构化集成电路器件
公开(公告)号：US20070188188A1
公开(公告)日：2007-08-16
申请号：US11739538
申请日：2007-04-24
申请人： Zvi Or-Bach , Ze'ev Wurman , Adam Levinthal , Laurence Cooke , Stan Mihelcic
发明人： Zvi Or-Bach , Ze'ev Wurman , Adam Levinthal , Laurence Cooke , Stan Mihelcic
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H01L2224/14 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311 , H03K19/17728 , H03K19/1774 , H03K19/17796
摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.
摘要翻译：可配置的逻辑阵列可以包括：多个逻辑单元，其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器，用于配置和测试阵列，其中定制可能都在单个通孔层上完成。

4. 发明授权

US07098528B2 Embedded redistribution interposer for footprint compatible chip package conversion 有权
标题翻译：嵌入式重新分配插入器用于脚印兼容芯片封装转换
公开(公告)号：US07098528B2
公开(公告)日：2006-08-29
申请号：US10744363
申请日：2003-12-22
申请人： Ronnie Vasishta , Stan Mihelcic
发明人： Ronnie Vasishta , Stan Mihelcic
IPC分类号： H01L29/40 , H01L23/31 , H01L23/48 , H05K1/14 , H05K3/34
CPC分类号： H01L23/49833 , H01L24/48 , H01L2224/05554 , H01L2224/48227 , H01L2924/00014 , H01L2924/10161 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embedded redistribution interposer is disclosed for providing footprint compatible chip package migration in which a die designed to be mounted into chip package is originally implemented using a first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package. According to the present invention, the embedded redistribution interposer includes a substrate having a plurality of bond pads on a top side thereof, wherein the redesigned die is mounted to the top of the interposer substrate, and the bottom of the interposer substrate is mounted to the substrate of the chip package. The redesigned die is connected to the redistribution interposer via a first set of electrical connections coupled between the die and the interposer bond pads. The redistribution interposer is then connected to the package via a second set of electrical connections coupled between the interposer bond pads and a package substrate, wherein signals from the die are redistributed in a manner that increases die fan-out without violating assembly rules, thereby eliminating the need to redesign the chip package to accommodate the redesigned die, resulting in a footprint compatible package.
摘要翻译：公开了一种嵌入式再分配插入器，用于提供占地面积兼容的芯片封装迁移，其中设计成安装到芯片封装中的裸片最初是使用第一种类型的硅平台实现的，并且随后被重新设计用于第二类型的硅平台，导致重新设计芯片的尺寸与原始裸片尺寸不同，不再适用于芯片封装中的安装。根据本发明，嵌入式再分配插入件包括在其顶侧具有多个接合焊盘的基板，其中，将重新设计的管芯安装到插入器基板的顶部，并且将内插器基板的底部安装到芯片封装的基板。重新设计的管芯通过耦合在管芯和插入器接合焊盘之间的第一组电连接件连接到再分配插入器。再分配插入器然后通过耦合在插入器接合焊盘和封装衬底之间的第二组电连接器连接到封装，其中来自模具的信号以不会违反组装规则增加模具扇出的方式重新分布，由此消除需要重新设计芯片封装以适应重新设计的裸片，从而产生一个占地面积兼容的封装。

5. 发明申请

US20060036987A1 Methods for optimizing package and silicon co-design of integrated circuit 有权
公开(公告)号：US20060036987A1
公开(公告)日：2006-02-16
申请号：US10918933
申请日：2004-08-16
申请人： Anwar Ali , Stan Mihelcic , James Monthie
发明人： Anwar Ali , Stan Mihelcic , James Monthie
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.

6. 发明授权

US07463062B2 Structured integrated circuit device 有权
标题翻译：结构化集成电路器件
公开(公告)号：US07463062B2
公开(公告)日：2008-12-09
申请号：US11739538
申请日：2007-04-24
申请人： Zvi Or-Bach , Ze'ev Wurman , Adam Levinthal , Laurence Cooke , Stan Mihelcic
发明人： Zvi Or-Bach , Ze'ev Wurman , Adam Levinthal , Laurence Cooke , Stan Mihelcic
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H01L2224/14 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311 , H03K19/17728 , H03K19/1774 , H03K19/17796
摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.
摘要翻译：可配置的逻辑阵列可以包括：多个逻辑单元，其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器，用于配置和测试阵列，其中定制可能都在单个通孔层上完成。

7. 发明申请

US20070187808A1 Customizable power and ground pins 审中-公开
标题翻译：可定制的电源和接地引脚
公开(公告)号：US20070187808A1
公开(公告)日：2007-08-16
申请号：US11354957
申请日：2006-02-16
申请人： Stan Mihelcic , Adam Levinthal , Laurence Cooke
发明人： Stan Mihelcic , Adam Levinthal , Laurence Cooke
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/49109 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01057 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/1517 , H01L2924/15312 , H01L2924/30107 , H01L2224/45099 , H01L2224/05599
摘要： A configurable logic array composed of: a multiplicity of logic cells, each containing look-up tables, a multiplicity of customizable I/O cells, each containing a multiplicity of pads; and a customizable via connection layer for customizing the cells and interconnect between them, may be constructed to include the option of customizing the I/O cells to act as power or ground pins. Assigning custom power and ground pins may depend on the types of I/O cells and package bonding options.
摘要翻译：一个可配置的逻辑阵列，由以下组成：多个逻辑单元，每个包含查找表，多个可定制I / O单元，每个单元包含多个焊盘; 并且可以构造用于定制单元和它们之间的互连的可定制的通孔连接层，以包括定制I / O单元以用作电源或接地引脚的选项。分配定制电源和接地引脚可能取决于I / O单元的类型和封装绑定选项。

8. 发明申请

US20050133935A1 Embedded redistribution interposer for footprint compatible chip package conversion 有权
标题翻译：嵌入式重新分配插入器用于脚印兼容芯片封装转换
公开(公告)号：US20050133935A1
公开(公告)日：2005-06-23
申请号：US10744363
申请日：2003-12-22
申请人： Ronnie Vasishta , Stan Mihelcic
发明人： Ronnie Vasishta , Stan Mihelcic
IPC分类号： H01L21/48 , H01L23/498 , H01L29/40
CPC分类号： H01L23/49833 , H01L24/48 , H01L2224/05554 , H01L2224/48227 , H01L2924/00014 , H01L2924/10161 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embedded redistribution interposer is disclosed for providing footprint compatible chip package migration in which a die designed to be mounted into chip package is originally implemented using a first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package. According to the present invention, the embedded redistribution interposer includes a substrate having a plurality of bond pads on a top side thereof, wherein the redesigned die is mounted to the top of the interposer substrate, and the bottom of the interposer substrate is mounted to the substrate of the chip package. The redesigned die is connected to the redistribution interposer via a first set of electrical connections coupled between the die and the interposer bond pads. The redistribution interposer is then connected to the package via a second set of electrical connections coupled between the interposer bond pads and a package substrate, wherein signals from the die are redistributed in a manner that increases die fan-out without violating assembly rules, thereby eliminating the need to redesign the chip package to accommodate the redesigned die, resulting in a footprint compatible package.
摘要翻译：公开了一种嵌入式再分配插入器，用于提供占地面积兼容的芯片封装迁移，其中设计成安装到芯片封装中的裸片最初是使用第一种类型的硅平台实现的，并且随后被重新设计用于第二类型的硅平台，导致重新设计芯片的尺寸与原始裸片尺寸不同，不再适用于芯片封装中的安装。根据本发明，嵌入式再分配插入件包括在其顶侧具有多个接合焊盘的基板，其中，将重新设计的管芯安装到插入器基板的顶部，并且将内插器基板的底部安装到芯片封装的基板。重新设计的管芯通过耦合在管芯和插入器接合焊盘之间的第一组电连接器连接到再分配插入器。再分配插入器然后通过耦合在插入器接合焊盘和封装衬底之间的第二组电连接器连接到封装，其中来自模具的信号以不会违反组装规则增加模具扇出的方式重新分布，由此消除需要重新设计芯片封装以适应重新设计的裸片，从而产生一个占地面积兼容的封装。

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