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1. 发明授权

US06963129B1 Multi-chip package having a contiguous heat spreader assembly 有权
标题翻译：具有连续散热器组件的多芯片封装
公开(公告)号：US06963129B1
公开(公告)日：2005-11-08
申请号：US10464178
申请日：2003-06-18
申请人： Thomas Evans , Stan Mihelcic , Leah M. Miller , Kumar Nagarajan , Edwin M. Fulcher
发明人： Thomas Evans , Stan Mihelcic , Leah M. Miller , Kumar Nagarajan , Edwin M. Fulcher
IPC分类号： H01L23/10 , H01L23/34 , H01L23/36 , H01L25/065
CPC分类号： H01L23/36 , H01L25/0655 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16195 , H01L2924/19105
摘要： A system and method are provided for forming a multi-chip package. The multi-chip package includes a multi-layer substrate and a heat spreader of single, unibody construction. At least two integrated circuits are coupled between the multi-layer substrate and the heat spreader. The integrated circuits are spaced from one another to allow airflow between those circuits and a portion of the underside surface of the heat spreader. Depending on the layout of the package, a passive device can also be placed in the space between integrated circuits. The passive device extends upward a spaced distance from the underneath surface of the heat spreader so as not to block the airflow therebetween. The multi-chip package can accommodate integrated circuits that are either all packaged, all unpackaged, or a combination of each. If packaged and unpackaged integrated circuits are placed on the multi-layer substrate, the heat spreader can extend in two separate planes to accommodate the different thicknesses of those packaged and unpackaged integrated circuits. Alternatively, a second heat spreader can be placed on a relatively thin integrated circuit so that the upper surface of the second heat spreader is coplanar with an upper surface of a relatively thick integrated circuit. This will allow a planar heat spreader to be arranged across the thick integrated circuit and the second heat spreader. In all instances, however, the heat spreader extends as a single, contiguous unibody element across the entire multi-chip package.
摘要翻译：提供了一种用于形成多芯片封装的系统和方法。多芯片封装包括多层基板和单一单体结构的散热器。至少两个集成电路耦合在多层基板和散热器之间。集成电路彼此间隔开，以允许这些电路之间的气流和散热器的下表面的一部分。根据封装的布局，无源器件也可放置在集成电路之间的空间中。被动装置从散热器的下表面向上延伸一定距离，以便不阻挡散热器之间的气流。多芯片封装可以容纳所有封装，所有未封装的封装或各自的组合的集成电路。如果封装和未封装的集成电路放置在多层基板上，散热器可以在两个独立的平面中延伸，以适应那些封装和未封装的集成电路的不同厚度。或者，可以将第二散热器放置在相对薄的集成电路上，使得第二散热器的上表面与相对较厚的集成电路的上表面共面。这将允许平面散热器布置在厚集成电路和第二散热器之间。然而，在所有情况下，散热器在整个多芯片封装上延伸为单个，连续的一体元件。

2. 发明授权

US07473583B1 Integrated circuit having a lid and method of employing a lid on an integrated circuit 有权
标题翻译：具有盖的集成电路和在集成电路上采用盖的方法
公开(公告)号：US07473583B1
公开(公告)日：2009-01-06
申请号：US11657191
申请日：2007-01-23
申请人： Kumar Nagarajan
发明人： Kumar Nagarajan
IPC分类号： H01L21/00
CPC分类号： H01L23/10 , H01L21/50 , H01L23/055 , H01L23/49816 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/16151 , H01L2924/16152 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/00
摘要： The present invention relates to a lid for an integrated circuit. According to one embodiment, an integrated circuit having a lid comprises a substrate having a flat surface and extending a first length and a lid having a recess and a foot portion. The lid generally has a second length shorter than the first length, and is positioned on the flat surface of the substrate. Finally, a bonding agent is positioned on the flat surface adjacent the foot portion of the lid. According to an alternate embodiment, a second component is positioned on the substrate outside the foot portion, and an adhesive seal is positioned on the substrate adjacent the foot and covering the component. A method of securing a lid to an integrated circuit is also disclosed.
摘要翻译：本发明涉及一种用于集成电路的盖子。根据一个实施例，具有盖的集成电路包括具有平坦表面并且延伸第一长度的基板和具有凹部和底脚部分的盖。盖通常具有比第一长度短的第二长度，并且位于基板的平坦表面上。最后，接合剂位于邻近盖的脚部的平坦表面上。根据替代实施例，第二部件位于基部外部的基部上，并且粘合密封件位于邻近脚部并覆盖部件的基底上。还公开了将盖固定到集成电路的方法。

3. 发明授权

US06911736B2 Electrostatic discharge protection 有权
标题翻译：静电放电保护
公开(公告)号：US06911736B2
公开(公告)日：2005-06-28
申请号：US10456281
申请日：2003-06-06
申请人： Kumar Nagarajan
发明人： Kumar Nagarajan
IPC分类号： H01L23/498 , H01L23/50 , H01L23/538 , H01L23/52
CPC分类号： H01L23/60 , H01L23/49816 , H01L23/50 , H01L23/5382 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： A package substrate that is adapted to receive at least one subject integrated circuit having a subject contact pattern, where the subject integrated circuit is selected from a design set of integrated circuits. The package substrate has an upper surface with electrically conductive bump contacts in a bump array. The bump array is configured to provide electrical connections to all possible integrated circuit contact patterns in the design set of integrated circuits. A lower surface of the package substrate has electrically conductive ball contacts in a ball array. One each of the bump contacts is electrically connected to one each of the ball contacts through the package substrate. An electrically conductive ground plane is disposed between the upper surface and the lower surface. Grounding contacts are disposed adjacent the ball contacts, where the grounding contacts are electrically connected to the ground plane. The grounding contacts are adapted to electrically short a given ball contact to the ground plane when the bump contact electrically connected to the given ball contact is not used by the subject contact pattern of the subject integrated circuit.
摘要翻译：适用于接收至少一个具有主题接触图案的被摄体集成电路的封装基板，其中所述主体集成电路从集成电路的设计集合中选择。封装衬底具有在凸起阵列中具有导电凸起接触的上表面。凸块阵列被配置为提供与集成电路的设计集合中的所有可能的集成电路接触图案的电连接。封装衬底的下表面具有球阵列中的导电球接触。每个凸块触点中的每一个通过封装基板电连接到每个滚珠触点。导电接地平面设置在上表面和下表面之间。接地触点设置在球触点附近，其中接地触头电连接到接地平面。接地触头适合于当与主体集成电路的主体接触图案不使用电连接到给定球接触点的凸点接触时，将给定的球接触电地短路到接地平面。

4. 发明授权

US06639321B1 Balanced coefficient of thermal expansion for flip chip ball grid array 有权
标题翻译：倒装芯片球栅阵列的平衡热膨胀系数
公开(公告)号：US06639321B1
公开(公告)日：2003-10-28
申请号：US09680759
申请日：2000-10-06
申请人： Kumar Nagarajan , Zafer Kutlu , Shirish Shah
发明人： Kumar Nagarajan , Zafer Kutlu , Shirish Shah
IPC分类号： H01L2940
CPC分类号： H01L21/563 , H01L23/3114 , H01L23/3128 , H01L24/29 , H01L24/83 , H01L2224/05568 , H01L2224/05569 , H01L2224/05573 , H01L2224/13025 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/83192 , H01L2224/83194 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/05599 , H01L2224/05099
摘要： A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
摘要翻译：倒装芯片球栅阵列封装包括具有从晶片厚度减小的管芯厚度的薄管芯，以减少薄管芯和基板之间的热膨胀系数的失配; 多个薄膜层，其形成在所述薄模上，其中所述多个薄膜层中的每一个具有大于所述薄模的热膨胀系数，并且小于所述基板的热膨胀系数; 以及形成在薄模上的多个晶片凸块，用于在薄模和基板之间进行电接触。

5. 发明授权

US08841752B1 Semiconductor structure and method for interconnection of integrated circuits 有权
标题翻译：集成电路互连的半导体结构和方法
公开(公告)号：US08841752B1
公开(公告)日：2014-09-23
申请号：US13246728
申请日：2011-09-27
申请人： Raghunandan Chaware , Kumar Nagarajan
发明人： Raghunandan Chaware , Kumar Nagarajan
IPC分类号： H01L23/544
CPC分类号： H01L23/10 , H01L23/49827 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2224/13101 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2224/83855 , H01L2224/92125 , H01L2924/15174 , H01L2924/15311 , H01L2924/014 , H01L2924/00014
摘要： In one or more embodiments, a semiconductor structure is provided that includes a plurality of interposer dice on an un-singulated segment of a semiconductor wafer. Scribe lanes circumscribing each of the plurality of interposer dice have widths of at least 2.5% of the width of each interposer die. Each interposer die includes a first contact array formed on a first side of the interposer die, a plurality of vias formed through the interposer die, one or more wiring layers formed on the first side of the interposer die and electrically coupling the first contact array to the plurality of vias, and a second contact array formed on a second side of the interposer die and electrically coupled to the plurality of vias.
摘要翻译：在一个或多个实施例中，提供了半导体结构，其在半导体晶片的未分割段上包括多个插入物晶片。限定多个中介体骰子中的每一个的划线通道具有至少每个插入器管芯宽度的2.5％的宽度。每个插入器管芯包括形成在插入器管芯的第一侧上的第一接触阵列，通过插入器管芯形成的多个通孔，形成在插入器管芯的第一侧上的一个或多个布线层，并将第一接触阵列电耦合到多个通孔，以及形成在插入器管芯的第二侧上并电耦合到多个通孔的第二接触阵列。

6. 发明授权

US08084297B1 Method of implementing a capacitor in an integrated circuit 有权
标题翻译：在集成电路中实现电容器的方法
公开(公告)号：US08084297B1
公开(公告)日：2011-12-27
申请号：US12851522
申请日：2010-08-05
申请人： Mukul Joshi , Kumar Nagarajan
发明人： Mukul Joshi , Kumar Nagarajan
IPC分类号： H01L21/00
CPC分类号： H01L23/50 , H01L23/04 , H01L23/10 , H01L23/642 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/01322 , H01L2924/15192 , H01L2924/15311 , H01L2924/16251 , H01L2924/19041 , H01L2924/19103 , H01L2924/19105 , H01L2924/3011 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.
摘要翻译：公开了一种在集成电路封装中实现电容器的方法。该方法包括将电容器耦合到集成电路封装的衬底的第一表面; 将集成电路管芯定位在电容器上，其中集成电路管芯具有第一多个焊料凸块和由没有焊料凸块的区域分开的第二多个焊料凸块; 将所述集成电路管芯连接到所述电容器上的所述衬底的所述第一表面，其中，所述没有焊料凸点的区域位于所述电容器上方; 并封装集成电路管芯和电容器。

7. 发明授权

US07187077B1 Integrated circuit having a lid and method of employing a lid on an integrated circuit 有权
标题翻译：具有盖的集成电路和在集成电路上采用盖的方法
公开(公告)号：US07187077B1
公开(公告)日：2007-03-06
申请号：US10805112
申请日：2004-03-19
申请人： Kumar Nagarajan
发明人： Kumar Nagarajan
IPC分类号： H01L23/04
CPC分类号： H01L23/10 , H01L21/50 , H01L23/055 , H01L23/49816 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/16151 , H01L2924/16152 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/00
摘要： The present invention relates to a lid for an integrated circuit. According to one embodiment, an integrated circuit having a lid comprises a substrate having a flat surface and extending a first length and a lid having a recess and a foot portion. The lid generally has a second length shorter than the first length, and is positioned on the flat surface of the substrate. Finally, a bonding agent is positioned on the flat surface adjacent the foot portion of the lid. According to an alternate embodiment, a second component is positioned on the substrate outside the foot portion, and an adhesive seal is positioned on the substrate adjacent the foot and covering the component. A method of securing a lid to an integrated circuit is also disclosed.
摘要翻译：本发明涉及一种用于集成电路的盖子。根据一个实施例，具有盖的集成电路包括具有平坦表面并且延伸第一长度的基板和具有凹部和底脚部分的盖。盖通常具有比第一长度短的第二长度，并且位于基板的平坦表面上。最后，接合剂位于邻近盖的脚部的平坦表面上。根据替代实施例，第二部件位于基部外部的基部上，并且粘合密封件位于邻近脚部并覆盖部件的基底上。还公开了将盖固定到集成电路的方法。

8. 发明授权

US06825066B2 Stiffener design 有权
标题翻译：加固设计
公开(公告)号：US06825066B2
公开(公告)日：2004-11-30
申请号：US10308310
申请日：2002-12-03
申请人： Yogendra Ranade , Anand Govind , Kumar Nagarajan , Farshad Ghahghahi , Aritharan Thurairajaratnam
发明人： Yogendra Ranade , Anand Govind , Kumar Nagarajan , Farshad Ghahghahi , Aritharan Thurairajaratnam
IPC分类号： H01L2144
CPC分类号： H01L23/04 , H01L23/50 , H01L25/165 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses. Because the major interior apertures does not need to be large enough to fit both the monolithic integrated circuit and the secondary circuit structure, there is more stiffener material available to provide structural support than there would be if the major interior aperture was large enough to fit both the monolithic integrated circuit and the secondary circuit structure.
摘要翻译：用于加强封装集成电路的加强件。加强件包括刚性平面元件，其具有用于结合到封装基板的第一表面。刚性平面元件形成用于在集成电路的所有侧面上接收和围绕集成电路的主要内部孔。刚性平面元件还形成次要内孔，用于在次级电路结构的至少三侧上接收和围绕次级电路结构。以这种方式，加强件提供对集成电路封装的结构支撑，其降低并优选地消除了衬底封装在其加热并经受其它应力时的扭曲和翘曲。因为主要内部孔径不需要足够大以适合单片集成电路和次级电路结构，所以有更多的加强材料可用于提供结构支撑，如果主要内部孔径足够大以适合于两者单片集成电路和二次电路结构。

9. 发明授权

US06320127B1 Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package 有权
标题翻译：用于减少电子部件封装的底部填充层中的空隙发生率的方法和结构
公开(公告)号：US06320127B1
公开(公告)日：2001-11-20
申请号：US09465425
申请日：1999-12-20
申请人： Kumar Nagarajan , Sarathy Rajagopalan
发明人： Kumar Nagarajan , Sarathy Rajagopalan
IPC分类号： H05K506
CPC分类号： H01L21/563 , H01L2224/73203 , H01L2924/09701 , H01L2924/10253 , H01L2924/00
摘要： A packaging substrate includes a plurality of bonding pads and a plurality of gutters formed thereon. A die having conductive bumps on an electrically active surface thereof is positioned such that the conductive bumps of the die are electrically connected to the bonding pads of the packaging substrate. An underfill material fills the underfill space between the packaging substrate and the die to complete the structure. The plurality of gutters creates a linear flow front of the underfill material as it flows across the underfill space.
摘要翻译：封装基板包括多个接合焊盘和形成在其上的多个沟槽。在其电活性表面上具有导电凸块的模具被定位成使得模具的导电凸块电连接到封装衬底的焊盘。底部填充材料填充包装基板和模具之间的底部填充空间以完成该结构。当底部填充材料流过底部填充空间时，多个水槽产生底部填充材料的线性流动前部。

10. 发明授权

US6133064A Flip chip ball grid array package with laminated substrate 有权
标题翻译：倒装芯片球栅阵列封装与层压基板
公开(公告)号：US6133064A
公开(公告)日：2000-10-17
申请号：US322064
申请日：1999-05-27
申请人： Kumar Nagarajan , Kishor Desai
发明人： Kumar Nagarajan , Kishor Desai
IPC分类号： H01L21/56 , H01L23/42 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/42 , H01L21/563 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/15151 , H01L2924/15311 , H01L2924/16195
摘要： Methods and apparatus pertaining to flip chip ball grid array packages are disclosed. A substrate comprises a base layer with a dielectric laminated thereon such that a cavity in the dielectric exposes the base layer. A die is then mounted to the exposed portion of the base layer. Preferably, an upper portion of the dielectric forms a frame for receiving a heat spreader.
摘要翻译：公开了与倒装芯片球栅阵列封装相关的方法和装置。衬底包括其上具有电介质的基底层，使得电介质中的空腔暴露于基底层。然后将模具安装到基层的暴露部分。优选地，电介质的上部形成用于接收散热器的框架。

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