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1. 发明授权

US07853747B2 Method and system for using an external bus controller in embedded disk controllers 有权
标题翻译：在嵌入式磁盘控制器中使用外部总线控制器的方法和系统
公开(公告)号：US07853747B2
公开(公告)日：2010-12-14
申请号：US11803458
申请日：2007-05-15
申请人： Larry L. Byers , Joseba M. Desubijana , Gary R. Robeck , Fredarico E. Dutton
发明人： Larry L. Byers , Joseba M. Desubijana , Gary R. Robeck , Fredarico E. Dutton
IPC分类号： G06F13/14
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： An embedded disk controller comprises a first processor in communication with a first bus and a second processor in communication with a second bus. An external bus controller (“EBC”) is located on the embedded disk controller, is coupled to an external bus and to at least one of the first bus and the second bus, and manages a plurality of memory devices external to the embedded disk controller via the external bus. A first one of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second one of the plurality of memory devices.
摘要翻译：嵌入式盘控制器包括与第一总线通信的第一处理器和与第二总线通信的第二处理器。外部总线控制器（“EBC”）位于嵌入式磁盘控制器上，耦合到外部总线和第一总线和第二总线中的至少一个，并管理嵌入式磁盘控制器外部的多个存储器件通过外部总线。多个存储器件中的第一个具有与多个存储器件中的第二个不同的定时特性和不同数据宽度中的至少一个。

2. 发明授权

US07080188B2 Method and system for embedded disk controllers 有权
标题翻译：嵌入式磁盘控制器的方法和系统
公开(公告)号：US07080188B2
公开(公告)日：2006-07-18
申请号：US10385022
申请日：2003-03-10
申请人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
发明人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
IPC分类号： G06F13/36 , G06F13/24
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.
摘要翻译：提供了一种嵌入式磁盘控制器的系统。该系统包括可操作地耦合到高性能总线的第一主处理器; 操作地耦合到外围总线的第二处理器; 高性能和外设总线之间的接口桥; 外部总线控制器，耦合到高性能总线，并通过外部总线接口可操作地耦合到外部设备; 中断控制器模块，其可以向第一主处理器产生快速中断; 耦合到高性能和外围总线的历史模块，用于监视总线活动; 以及伺服控制器，其通过伺服控制器接口耦合到第二处理器，并向第二处理器提供实时伺服控制器信息。第二处理器可以是通过接口可操作地耦合到第一主处理器的数字信号处理器。

3. 发明授权

US5142629A System for interconnecting MSUs to a computer system 失效
标题翻译：将MSU与计算机系统相互连接的系统
公开(公告)号：US5142629A
公开(公告)日：1992-08-25
申请号：US403640
申请日：1989-09-06
申请人： Larry L. Byers , Joseba M. Desubijana
发明人： Larry L. Byers , Joseba M. Desubijana
IPC分类号： G06F13/40 , G06F15/173
CPC分类号： G06F15/17368 , G06F13/4022
摘要： An improved system for interconnecting main storage units is provided wherein each main storage unit is provided with a support control card and each support control card is provided with interface connection means comprising X-1 number of interfaces where X is a value equal to the number of MSUs. And means for enabling the connection of the interfaces between different pairs of MSUs to operably connect any number of said X number of MSUs to a plurality of data processors employing X(X-1)/2 pairs of cables.
摘要翻译：提供了一种用于互连主存储单元的改进的系统，其中每个主存储单元设置有支持控制卡，并且每个支持控制卡设置有包括X-1个接口的接口连接装置，其中X等于 MSU。以及用于使得能够连接不同成对MSU之间的接口的装置可操作地将任何数量的所述X个数量的MSU连接到采用X（X-1）/ 2对电缆的多个数据处理器。

4. 发明授权

US07099963B2 Method and system for monitoring embedded disk controller components 有权
标题翻译：监控嵌入式磁盘控制器组件的方法和系统
公开(公告)号：US07099963B2
公开(公告)日：2006-08-29
申请号：US10385042
申请日：2003-03-10
申请人： Larry L. Byers , Joseba M. Desubijana , Gary R. Robeck , William W. Dennin
发明人： Larry L. Byers , Joseba M. Desubijana , Gary R. Robeck , William W. Dennin
IPC分类号： G06F11/34
CPC分类号： G06F11/3034 , G06F11/3072 , G11B27/36
摘要： A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a second bus is provided. The history module includes an event control module that receives break point conditions that stops the history module from recording information of a component; and a first register that allows selection or-de-selection of certain components in the embedded disk controller. The first register can also store a trigger mode value, which specifies a number of entries that are made in history module buffer(s) after a break point condition is detected.
摘要翻译：提供了一种用于监视嵌入式盘控制器中的多个组件的历史模块，其中操作上耦合到第一总线的第一主处理器和可操作地耦合到第二总线的第二处理器。历史模块包括事件控制模块，其接收使历史模块停止记录组件信息的断点条件; 以及允许在嵌入式磁盘控制器中选择或取消某些组件的第一寄存器。第一个寄存器还可以存储触发模式值，该值指定在检测到断点条件后在历史模块缓冲区中进行的条目数。

5. 发明授权

US5423030A Bus station abort detection 失效
标题翻译：车站中止检测
公开(公告)号：US5423030A
公开(公告)日：1995-06-06
申请号：US120093
申请日：1993-09-13
申请人： Larry L. Byers , Joseba M. Desubijana , Wayne A. Michaelson
发明人： Larry L. Byers , Joseba M. Desubijana , Wayne A. Michaelson
IPC分类号： G06F11/00 , G06F11/07 , G06F11/34
CPC分类号： G06F11/0745 , G06F11/0751 , G06F11/0793
摘要： A bus control and error detection system is provided for a bus system in which data and address signals are transferred between a microsequencer and a number of operational stations which are coupled to the bus. Tri-state drivers are employed in the microsequencer and in the stations which are constructed such that two of the three states of these tri-state drivers are utilized to provide the two states of binary logic operation, and the third state is a high impedance state that protects the components that are coupled to the bus during predefined abort condition which are detected in the system. An abort detection circuit is included in each of the operational stations which is coupled to receive control signals from the microsequencer and which is constructed to emit an ABORT signal output to the microsequencer when the control signals indicate that an abort condition has occurred for the associated operational station. The ABORT signal causes the tri-state driver in the microsequencer to switch to its high impedance state and the microsequencer and transmit LOCK BUS signals to all of the operational stations in order to switch their tri-state drivers to their high impedance states.
摘要翻译：为总线系统提供总线控制和错误检测系统，其中数据和地址信号在微定序器和耦合到总线的多个操作站之间传送。三态驱动器被采用在微定序器中和在这些被构造为使得三态驱动器的三种状态中的两个被用于提供二态逻辑运算的两种状态的站中，并且第三状态是高阻抗状态其在系统中检测到的预定中止条件期间保护耦合到总线的组件。在每个操作站中包括中止检测电路，其被耦合以从微定序器接收控制信号，并且当控制信号指示已经针对相关联的操作发生了中止条件时被构造为发射输出到微定序器的ABORT信号站。 ABORT信号使微定序器中的三态驱动器切换到其高阻抗状态，并将微锁定器发送LOCK BUS信号到所有操作站，以便将它们的三态驱动器切换到高阻状态。

6. 发明授权

US4962501A Bus data transmission verification system 失效
标题翻译：总线数据传输验证系统
公开(公告)号：US4962501A
公开(公告)日：1990-10-09
申请号：US244187
申请日：1988-09-13
申请人： Larry L. Byers , James H. Scheuneman , Joseba M. Desubijana
发明人： Larry L. Byers , James H. Scheuneman , Joseba M. Desubijana
IPC分类号： G06F11/10 , G06F11/267 , G06F13/00
CPC分类号： G06F11/10 , G06F11/2215
摘要： A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.
摘要翻译：多个发送和接收元件耦合在读和总线之间。将发送和接收元件连接到总线的通信路径分别设置有与其串联的故障指示电路。每个所述故障指示电路具有逻辑门控装置，其包括用于数据字节的每个比特的位寄存器和奇偶校验位。位寄存器装置的输出耦合到隔离驱动器，隔离驱动器又连接到奇偶校验电路和总线，用于指示出现在数据字的字节中的错误，而不降低或延迟与所述读和写总线之间的数据传输。

7. 发明授权

US4953167A Data bus enable verification logic 失效
标题翻译：数据总线使能验证逻辑
公开(公告)号：US4953167A
公开(公告)日：1990-08-28
申请号：US244190
申请日：1988-09-13
申请人： Larry L. Byers , Wayne A. Michaelson , Joseba M. Desubijana
发明人： Larry L. Byers , Wayne A. Michaelson , Joseba M. Desubijana
IPC分类号： G06F13/00 , G06F11/08
CPC分类号： G06F11/085
摘要： Logic checking circuits are provided for verifying whether or not the data bus enable logic circuits are operating properly in response to operational commands to transmit or to NOT transmit data. The transmit latches in the bus interface logic circuits are continuously monitored to determine if they are set or NOT set in a position to enable transmission of data or NOT to enable transmission of data to a bus. Transmit gating circuit means are couple to the output of said transmit latches for determining if all of the transmit latches are in the same state and are in the state ordered by the central controller, and for determining whether the state ordered by the central controller occurs in the exact time period during which the command to transmit should be executed.
摘要翻译：逻辑检查电路被提供用于验证数据总线使能逻辑电路是否响应于要发送或不发送数据的操作命令而正常工作。总线接口逻辑电路中的发送锁存器被连续地监视，以确定它们是被设置还是不被设置在能够传输数据或不使数据传输到总线的位置。发送门控电路装置耦合到所述发送锁存器的输出端，用于确定所有发送锁存器是否处于相同状态并且处于由中央控制器排序的状态，并且用于确定由中央控制器排序的状态是否发生在应执行发送命令的确切时间段。

8. 发明授权

US5488702A Data block check sequence generation and validation in a file cache system 失效
标题翻译：在文件缓存系统中的数据块检查序列生成和验证
公开(公告)号：US5488702A
公开(公告)日：1996-01-30
申请号：US233199
申请日：1994-04-26
申请人： Larry L. Byers , Joseba M. Desubijana , Wayne A. Michaelson
发明人： Larry L. Byers , Joseba M. Desubijana , Wayne A. Michaelson
IPC分类号： G06F11/10 , G06F11/34
CPC分类号： G06F11/1004
摘要： A system and method for detecting errors during the storage and retrieval of file information between a file cache system and a host computer system utilizes a block check sequence key as redundant data included in each block of file data transferred. The block check sequence key is generated by key generation logic and accompanies each block of file data stored in the file cache system by the host computer system. The block check sequence key is a compressed representation of the data within the selected block, as well as unique file and block identification information supplied by the requester of the write operation. When the block is retrieved from the file cache system, the system generates a new block check sequence key based on the data within the retrieved block and the unique file and block identification information supplied by the requester of the read operation. Validation logic ensures that if the retrieved key and the newly generated key does not match, an error signal is activated.
摘要翻译：用于在文件高速缓存系统和主机系统之间的文件信息的存储和检索期间检测错误的系统和方法利用块校验序列密钥作为包含在传送的每个文件数据块中的冗余数据。块检查序列密钥由密钥生成逻辑生成，并且由主计算机系统伴随存储在文件高速缓存系统中的每个文件数据块。块检查序列密钥是所选块内的数据的压缩表示，以及由写操作的请求者提供的唯一的文件和块标识信息。当从文件缓存系统检索到该块时，系统基于检索到的块内的数据和由读取操作的请求者提供的唯一文件和块识别信息生成新的块校验序列密钥。验证逻辑确保如果检索到的密钥和新生成的密钥不匹配，则会激活错误信号。

9. 发明授权

US5168555A Initial program load control 失效
标题翻译：初始程序加载控制
公开(公告)号：US5168555A
公开(公告)日：1992-12-01
申请号：US403637
申请日：1989-09-06
申请人： Larry L. Byers , Joseba M. Desubijana
发明人： Larry L. Byers , Joseba M. Desubijana
IPC分类号： G06F9/445 , G06F15/177
CPC分类号： G06F15/177 , G06F9/4405
摘要： A multi-processing system of the type having a plurality of MSUs is provided with a support controller in each MSU. Each of the MSUs is provided with a plurality of the interface registers, one for each associated MSU to be connected to the master MSU. Each support controller in each MSU is provided with an initial program load (IPL) controller and each IPL controller is provided with a scan settable control coupled to an external keyboard or console which permits unique scan settable information to be loaded into the IPL controller for setting the interface registers and for interconnecting the MSUs in a desired multi-processing configuration.
摘要翻译：具有多个MSU的多处理系统在每个MSU中设置有支持控制器。每个MSU设置有多个接口寄存器，每个相关联的MSU一个用于连接到主MSU。每个MSU中的每个支持控制器具有初始程序加载（IPL）控制器，并且每个IPL控制器被提供有耦合到外部键盘或控制台的扫描可设置控制器，其允许将唯一的可扫描可设置信息加载到IPL控制器中用于设置接口注册并用于以期望的多处理配置来互连MSU。

10. 发明授权

US08788641B1 Small form factor interface module 有权
标题翻译：小尺寸接口模块
公开(公告)号：US08788641B1
公开(公告)日：2014-07-22
申请号：US11936631
申请日：2007-11-07
申请人： Joseba M. Desubijana , Larry L. Byers , Gary R. Robeck
发明人： Joseba M. Desubijana , Larry L. Byers , Gary R. Robeck
IPC分类号： G06F15/173
CPC分类号： G06F13/126 , Y02D10/14
摘要： Systems, apparatuses, and methods for an interface module to interface with an enclosure services processor are described herein. The interface module may include one or more state machines configured to provide an enclosure service operation. Provision of this enclosure service operation may be at least partially unsupervised by a control processor requesting the enclosure service operation. Other embodiments may be described and claimed.
摘要翻译：本文描述了用于接口模块与机箱服务处理器接口的系统，设备和方法。接口模块可以包括被配置为提供机箱服务操作的一个或多个状态机。可以由控制处理器至少部分地提供这种机箱服务操作，该控制处理器请求机箱服务操作。可以描述和要求保护其他实施例。

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