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1. 发明授权

US07080188B2 Method and system for embedded disk controllers 有权
标题翻译：嵌入式磁盘控制器的方法和系统
公开(公告)号：US07080188B2
公开(公告)日：2006-07-18
申请号：US10385022
申请日：2003-03-10
申请人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
发明人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
IPC分类号： G06F13/36 , G06F13/24
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.
摘要翻译：提供了一种嵌入式磁盘控制器的系统。该系统包括可操作地耦合到高性能总线的第一主处理器; 操作地耦合到外围总线的第二处理器; 高性能和外设总线之间的接口桥; 外部总线控制器，耦合到高性能总线，并通过外部总线接口可操作地耦合到外部设备; 中断控制器模块，其可以向第一主处理器产生快速中断; 耦合到高性能和外围总线的历史模块，用于监视总线活动; 以及伺服控制器，其通过伺服控制器接口耦合到第二处理器，并向第二处理器提供实时伺服控制器信息。第二处理器可以是通过接口可操作地耦合到第一主处理器的数字信号处理器。

2. 发明授权

US08270107B1 Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive 有权
标题翻译：用于磁盘驱动器的控制器中不归零（NRZ）线性反馈移位寄存器（LFSR）的累加器
公开(公告)号：US08270107B1
公开(公告)日：2012-09-18
申请号：US13246960
申请日：2011-09-28
申请人： Lim Hudiono , Paul B. Ricci
发明人： Lim Hudiono , Paul B. Ricci
IPC分类号： G11B27/36
CPC分类号： G11B5/455 , G11B19/048 , G11B27/36 , G11B2220/2516
摘要： A disk controller for a hard disk drive includes a disk formatter interfaced via an NRZ bus to a read channel for the disk. The disk formatter includes an LFSR accumulator coupled to the NRZ bus, as well as an LSFR generator that generates synthetic test data for the disk formatter. Under control of a test flag which signifies a test mode, the LSFR generator generates synthetic test data, which is used by the disk formatter to drive the NRZ bus. The LSFR accumulator accumulates data on the NRZ bus, together with data on servo information and sector information. An interface is provided through which the accumulated information is provided to test equipment, for offline analysis of the accumulated information, so as to confirm proper operation of the disk subsystem and/or to detect failures therein.
摘要翻译：用于硬盘驱动器的盘控制器包括经由NRZ总线连接到盘的读通道的盘格式器。磁盘格式器包括耦合到NRZ总线的LFSR累加器，以及生成用于磁盘格式器的合成测试数据的LSFR发生器。在表示测试模式的测试标志的控制下，LSFR发生器产生合成测试数据，由磁盘格式器用于驱动NRZ总线。 LSFR累加器在NRZ总线上累加数据，以及伺服信息和扇区信息的数据。提供一个接口，通过该接口提供累积信息给测试设备，用于离线分析累积的信息，以确认磁盘子系统的正常运行和/或检测到其中的故障。

3. 发明授权

US5442754A Receiving control logic system for dual bus network 失效
标题翻译：接收双总线网络的控制逻辑系统
公开(公告)号：US5442754A
公开(公告)日：1995-08-15
申请号：US985662
申请日：1992-12-04
申请人： Wayne C. Datwyler , Paul B. Ricci
发明人： Wayne C. Datwyler , Paul B. Ricci
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A system for controlling and routing messages and data received from dual system busses, through a bus interface unit, to a protocol translation logic means and to a processor in a central processing module connected onto a dual system bus network. The processor operates at a first clock rate and on a single-word communication protocol while the translation logic means operates at a second rate and multiple-word communication protocol. The processor and translation logic are destination modules which receive the benefit of the receiving control logic system. The receiving control logic system also services external modules on the system bus in order to receive data and control the routing of data to the destination modules. Destination modules which are busy and not ready will cause the system to inform the external transmitting modules that they must retry their transmission. The system also checks the quality of the data on the system busses and informs the processor when errors have been incurred, in addition to informing the originating modules when a transmitted message has been completed.
摘要翻译：用于控制和路由从双系统总线接收的消息和数据通过总线接口单元传送到协议转换逻辑装置并连接到连接到双系统总线网络上的中央处理模块中的处理器的系统。处理器以第一时钟速率和单字通信协议操作，而转换逻辑装置以第二速率和多字通信协议操作。处理器和翻译逻辑是接收控制逻辑系统的好处的目标模块。接收控制逻辑系统还为系统总线上的外部模块提供服务，以便接收数据并控制数据到目标模块的路由。正在忙碌并且未准备好的目标模块将导致系统通知外部传输模块必须重试其传输。该系统还检查系统总线上的数据质量，并在发生错误时通知处理器，以及在发送的消息已经完成时通知发端模块。

4. 发明授权

US5444860A Translator system for message transfers between digital units operating on different message protocols and different clock rates 失效
标题翻译：用于在不同消息协议和不同时钟速率下工作的数字单元之间的消息传送的转换器系统
公开(公告)号：US5444860A
公开(公告)日：1995-08-22
申请号：US837174
申请日：1992-02-14
申请人： Wayne C. Datwyler , Paul B. Ricci
发明人： Wayne C. Datwyler , Paul B. Ricci
IPC分类号： G06F5/10 , G06F5/06
CPC分类号： G06F5/10
摘要： A message transfer system between digital modules where two or more digital modules operate on separate and different message lengths and clock frequencies and where, temporary storage buffer (translator unit) holds messages being transferred between the different digital modules and acts as a speed matching and word length matching buffer unit to permit compatible transfer of message words. Also, the transfer system recognizes when requests are outstanding from both digital modules and can discard a message from a requesting module. Each of the two or more separate digital modules is serviced by dual system busses providing for redundancy of data transfer operations.
摘要翻译：数字模块之间的消息传送系统，其中两个或多个数字模块在分离的和不同的消息长度和时钟频率上操作，并且其中临时存储缓冲器（转换器单元）保持在不同的数字模块之间传输的消息，并且作为速度匹配和字长度匹配缓冲单元，以允许消息字的兼容传输。此外，传送系统识别来自两个数字模块的请求何时未完成，并且可以从请求模块丢弃消息。两个或多个单独的数字模块中的每一个由双系统总线提供服务，以提供数据传输操作的冗余。

5. 发明授权

US07836379B1 Method for computing buffer ECC 有权
标题翻译：计算缓冲区ECC的方法
公开(公告)号：US07836379B1
公开(公告)日：2010-11-16
申请号：US11605797
申请日：2006-11-29
申请人： Paul B. Ricci , Mohammad M. Negahban , Yujun Si
发明人： Paul B. Ricci , Mohammad M. Negahban , Yujun Si
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/1076 , G06F2211/1059 , G06F2211/1088 , G06F2211/109
摘要： A system includes a receive module, a control module and a read module. The receive module receives a first block that includes first data, a first cyclic redundancy check (CRC) checksum, and a first error-correcting code (ECC) value. The first CRC checksum and the first ECC value include a logical block address (LBA). The control module generates a first derived CRC checksum based on the first data. The first derived CRC checksum does not include the LBA. The read module reads a second block from a parity disk. The second block includes parity data, a second CRC checksum, and a second ECC value. The second CRC checksum and the second ECC value include the LBA.
摘要翻译：系统包括接收模块，控制模块和读取模块。接收模块接收包括第一数据，第一循环冗余校验（CRC）校验和和第一纠错码（ECC）值的第一块。第一个CRC校验和和第一个ECC值包括逻辑块地址（LBA）。控制模块基于第一数据生成第一导出的CRC校验和。第一个派生的CRC校验和不包括LBA。读取模块从奇偶校验磁盘读取第二个块。第二块包括奇偶校验数据，第二CRC校验和和第二ECC值。第二个CRC校验和和第二个ECC值包括LBA。

6. 发明授权

US5404462A Dual bus interface transfer system for central processing module 失效
标题翻译：双总线接口传输系统，用于中央处理模块
公开(公告)号：US5404462A
公开(公告)日：1995-04-04
申请号：US963304
申请日：1992-10-16
申请人： Wayne C. Datwyler , Paul B. Ricci
发明人： Wayne C. Datwyler , Paul B. Ricci
IPC分类号： G06F11/20 , G06F13/38 , H01J13/00 , G06F9/455
CPC分类号： G06F11/2007 , G06F13/385
摘要： A bus interface transfer system enables communication to/from dual busses to multiple resource units which include a central processor module and a translation logic unit which permits data transfer between systems having different protocols and different clock rates.
摘要翻译：总线接口传输系统使得能够从双总线通信到多个资源单元，其包括中央处理器模块和允许在具有不同协议和不同时钟速率的系统之间进行数据传输的转换逻辑单元。

7. 发明授权

US5293621A Varying wait interval retry apparatus and method for preventing bus lockout 失效
标题翻译：改变等待间隔重试装置和防止总线锁定的方法
公开(公告)号：US5293621A
公开(公告)日：1994-03-08
申请号：US2566
申请日：1993-01-11
申请人： Theodore C. White , Jayesh V. Sheth , Paul B. Ricci , Dan T. Tran
发明人： Theodore C. White , Jayesh V. Sheth , Paul B. Ricci , Dan T. Tran
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G06F13/1689
摘要： A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.
摘要翻译：一种用于时分共享总线，多总线用户，计算机架构的用户总线锁定预防机制，其中总线用户具有专用高速缓存系统，当总线上发生写入存储器指令以执行高速缓存循环，以确定是否从主站缓存数据内存已被主内存覆盖。如果在重复高速缓存周期与用户的请求重试机制的周期之间发生同步，则用户可以被禁止使用总线。通过控制用户的重试机制根据不同的重试等待间隔的顺序重试请求来防止总线锁定。该序列包括具有长等待间隔交错的短等待间隔的脉冲串，序列以短等待间隔的脉冲串开始。第一和第二发生突发的等待间隔持续时间彼此交错。第二次发生长时间的等待时间长于首次发生的长时间等待。总线授予后，该序列终止。

8. 发明授权

US07559009B1 System and method for performing parity checks in disk storage systems 有权
标题翻译：在磁盘存储系统中执行奇偶校验的系统和方法
公开(公告)号：US07559009B1
公开(公告)日：2009-07-07
申请号：US11521979
申请日：2006-09-15
申请人： Paul B. Ricci
发明人： Paul B. Ricci
IPC分类号： G11B20/18
CPC分类号： G06F11/1076 , G06F2211/109 , G11B20/1833 , G11B2020/1843
摘要： A cyclic redundancy check (CRC) system for a storage controller comprises a memory that stores first sector data and a corresponding CRC non-zero seed value. A buffer control module includes a CRC module, calculates a CRC value of the first sector data with the CRC module, and combines the CRC value with the CRC non-zero seed value.
摘要翻译：用于存储控制器的循环冗余校验（CRC）系统包括存储第一扇区数据和对应的CRC非零种子值的存储器。缓冲器控制模块包括CRC模块，用CRC模块计算第一扇区数据的CRC值，并将CRC值与CRC非零种子值组合。

9. 发明授权

US07111228B1 System and method for performing parity checks in disk storage system 有权
标题翻译：在磁盘存储系统中执行奇偶校验的系统和方法
公开(公告)号：US07111228B1
公开(公告)日：2006-09-19
申请号：US10429495
申请日：2003-05-05
申请人： Paul B. Ricci
发明人： Paul B. Ricci
IPC分类号： G11B20/18 , H03M13/09
CPC分类号： G06F11/1076 , G06F2211/109 , G11B20/1833 , G11B2020/1843
摘要： A system for maintaining cyclic redundancy check (“CRC”) protection of XOR'ed data sectors includes a register that is initialized with a non-zero seed value used for generating sector CRC values. The system includes logic for combining CRC values of at least two sectors and storing a result of the combination modified with a non-zero seeded CRC value.
摘要翻译：用于维持异或数据扇区的循环冗余校验（“CRC”）保护的系统包括用用于产生扇区CRC值的非零种子值初始化的寄存器。该系统包括用于组合至少两个扇区的CRC值并存储以非零种子CRC值修改的组合结果的逻辑。

10. 发明授权

US5553263A Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory 失效
标题翻译：具有同步运行的高速缓存控制器的具有容错的缓存存储器系统处理不相交的存储器组
公开(公告)号：US5553263A
公开(公告)日：1996-09-03
申请号：US92835
申请日：1993-07-16
申请人： David M. Kalish , Saul Barajas , Paul B. Ricci
发明人： David M. Kalish , Saul Barajas , Paul B. Ricci
IPC分类号： G06F11/00 , G06F11/20 , G06F12/08 , G06F12/02 , G06F13/00
CPC分类号： G06F11/2017 , G06F12/0851
摘要： A processor cache memory system utilizes separate cache controllers for independently managing even and odd input address requests with the even and odd address requests being mapped into the respective controllers. Each cache controller includes tag RAM for storing address tags, including a field for storing the least significant address bit, so that the stored tags distinguish between the odd and even addresses. Upon failure of a cache controller, both the even and odd addresses are directed to the operational controller and the stored least significant bit address tag distinguishes between the odd and even input addresses to appropriately generate HIT/MISS signals. The controllers include block address counter logic for generating respective even and odd invalidation addresses for simultaneously performing invalidation cycles thereon when both controllers are operational. When a controller fails, the block address counter logic generates both even and odd block invalidation addresses in the operational controller.
摘要翻译：处理器高速缓冲存储器系统利用单独的高速缓存控制器来独立地管理偶数和奇数输入地址请求，偶数和奇数地址请求被映射到相应的控制器中。每个高速缓存控制器包括用于存储地址标签的标签RAM，包括用于存储最低有效地址位的字段，使得存储的标签区分奇数和偶数地址。在高速缓存控制器发生故障时，偶数和奇数地址都被定向到操作控制器，并且所存储的最低有效位地址标签区分奇数和偶数输入地址以适当地生成HIT / MISS信号。控制器包括块地址计数器逻辑，用于当两个控制器都可操作时，产生用于同时执行无效循环的相应偶数和奇数无效地址。当控制器出现故障时，块地址计数器逻辑在运算控制器中产生偶数和奇数块无效地址。

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