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1. 发明授权

US07848432B2 System and method for efficiently storing macroblocks in SD-RAM 失效
标题翻译：用于高效地存储SD-RAM中的宏块的系统和方法
公开(公告)号：US07848432B2
公开(公告)日：2010-12-07
申请号：US10716008
申请日：2003-11-18
申请人： Lakshman Ramakrishnan , Sathish Kumar Radhakrishnan , Brian Schoner , Darren Neuman
发明人： Lakshman Ramakrishnan , Sathish Kumar Radhakrishnan , Brian Schoner , Darren Neuman
IPC分类号： H04N7/12 , H04N7/18
CPC分类号： H04N19/423 , H04N19/61
摘要： Presented herein are systems and methods for efficiently storing macroblocks in DRAM. The macroblocks are stored contiguously allowing each macroblock to be written and overwritten in a single write transaction. Additionally, in one embodiment, as many as five macroblocks can be written or overwritten in a single write transaction.
摘要翻译：这里呈现的是用于在DRAM中有效地存储宏块的系统和方法。宏块被连续存储，允许在单个写入事务中写入和重写每个宏块。另外，在一个实施例中，多达五个宏块可以在单个写入事务中被写入或重写。

2. 发明授权

US07111111B2 Scheme for optimal settings for DDR interface 有权
标题翻译： DDR接口的最佳设置方案
公开(公告)号：US07111111B2
公开(公告)日：2006-09-19
申请号：US10716066
申请日：2003-11-18
申请人： Darren Neuman , Sathish Kumar Radhakrishnan , Jeffrey Fisher , Joshua Stults , Nitin Borle , Kaushik Bhattacharya
发明人： Darren Neuman , Sathish Kumar Radhakrishnan , Jeffrey Fisher , Joshua Stults , Nitin Borle , Kaushik Bhattacharya
IPC分类号： G06F12/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C2207/107 , G11C2207/2254
摘要： Methods of optimizing a plurality of numerically controlled delay lines (NCDLS) in a DDR memory controller are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: acquiring a plurality of statistics, the plurality of statistics defining an operating region for the DDR memory controller; and calculating optimal values for the plurality of NCDLs, the optimal values calculated using the plurality of statistics.
摘要翻译：本文给出了优化DDR存储器控制器中的多个数控延迟线（NCDLS）的方法。在一个实施例中，方法可以包括例如以下中的一个或多个：获取多个统计，所述多个统计定义了DDR存储器控制器的操作区域; 以及计算所述多个NCDL的最佳值，所述最优值使用所述多个统计量计算。

3. 发明申请

US20110276817A1 MEMORY POWER MANAGER 有权
标题翻译：内存电源管理器
公开(公告)号：US20110276817A1
公开(公告)日：2011-11-10
申请号：US12774479
申请日：2010-05-05
申请人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty
发明人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty
IPC分类号： G06F1/32 , G06F12/00 , G06F1/00
CPC分类号： G06F13/1668 , G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
摘要翻译：控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。然后将最高排名的客户端传递给定序器以允许请求的访问。时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。处理通过相关的逻辑电路并行（同时）在硬件中执行。

4. 发明授权

US07430680B2 System and method to align clock signals 失效
标题翻译：系统和方法来对齐时钟信号
公开(公告)号：US07430680B2
公开(公告)日：2008-09-30
申请号：US11169006
申请日：2005-06-29
申请人： Lionel J. D'Luna , Thomas A. Hughes , Sathish Kumar Radhakrishnan
发明人： Lionel J. D'Luna , Thomas A. Hughes , Sathish Kumar Radhakrishnan
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/12
摘要： A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal. These subsequent delay device clock signals are transmitted to the aligning device and to the sequencer before each transfer occurs.
摘要翻译：在它们之间的数据传输之前，系统和方法使用对准装置对准两个逻辑装置的时钟信号。在该示例中，对准装置在定序器将数据传送到存储装置之前将定序器的时钟信号与存储装置的时钟信号对准。对准装置包括相位检测器，其接收用于控制存储装置的第一参考时钟信号和用于控制定序器的延迟信号，并产生比较时钟信号。在用于控制与第一参考时钟信号相关的第二参考时钟信号的相位之前，对比较时钟信号进行滤波。相位控制的第二时钟信号是对准时钟信号，其被反馈到延迟器件以产生与存储器件时钟或第一参考时钟信号对准的一个或多个后续延迟器件时钟信号。在每次传送发生之前，这些后续的延迟装置时钟信号被发送到对准装置和定序器。

5. 发明授权

US08812889B2 Memory power manager 有权
标题翻译：内存电源管理器
公开(公告)号：US08812889B2
公开(公告)日：2014-08-19
申请号：US12774479
申请日：2010-05-05
申请人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty
发明人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty
IPC分类号： G06F1/26 , G06F1/32 , G06F13/16
CPC分类号： G06F13/1668 , G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
摘要翻译：控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。然后将最高排名的客户端传递给定序器以允许请求的访问。时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。处理通过相关的逻辑电路并行（同时）在硬件中执行。

6. 发明授权

US08022966B2 Video, audio and graphics decode, composite and display system 有权
标题翻译：视频，音频和图形解码，复合和显示系统
公开(公告)号：US08022966B2
公开(公告)日：2011-09-20
申请号：US12650361
申请日：2009-12-30
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar Radhakrishnan
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar Radhakrishnan
IPC分类号： G09G5/00 , G09G5/36 , H04N11/22 , H04N11/00 , H04L12/28
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译：视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。该系统将PES处理成数字音频，MPEG视频和消息数据。该系统能够同时解码多个MPEG SLICE。图形窗口并行混合，并使用alpha混合与视频混合。在图形处理期间，单端口SRAM被等价地用作双端口SRAM。视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。该系统包括一个内存控制器。该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。

7. 发明申请

US20110276766A1 CONFIGURABLE MEMORY CONTROLLER 审中-公开
标题翻译：可配置内存控制器
公开(公告)号：US20110276766A1
公开(公告)日：2011-11-10
申请号：US12774462
申请日：2010-05-05
申请人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty , Lance Flake , Vinay Bhasin
发明人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty , Lance Flake , Vinay Bhasin
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3215 , G06F13/1626 , H04W52/0274 , Y02D10/13 , Y02D10/14 , Y02D70/142 , Y02D70/144
摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
摘要翻译：控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。然后将最高排名的客户端传递给定序器以允许请求的访问。时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。处理通过相关的逻辑电路并行（同时）在硬件中执行。

8. 发明授权

US07246341B2 Byte slice based DDR timing closure 有权
标题翻译：基于字节片的DDR定时关闭
公开(公告)号：US07246341B2
公开(公告)日：2007-07-17
申请号：US10917693
申请日：2004-08-13
申请人： Lionel D'Luna , Tom Hughes , Sathish Kumar Radhakrishnan
发明人： Lionel D'Luna , Tom Hughes , Sathish Kumar Radhakrishnan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and placing the synthesized/laid out portion and the replicated portions in proximity to a corresponding plurality of pads.
摘要翻译：这里提出了一种用于基于字节片的DDR定时关闭的系统和方法。在一个实施例中，提出了一种用于合成/布置双数据速率存储器的方法，所述方法包括合成/布置双数据速率存储器的一部分; 复制该部分; 并将合成/布置的部分和复制部分放置在相应的多个焊盘附近。

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