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1. 发明授权

US06197706B1 Low temperature method to form low k dielectric 有权
标题翻译：低温方法形成低k电介质
公开(公告)号：US06197706B1
公开(公告)日：2001-03-06
申请号：US09607042
申请日：2000-06-30
申请人： Lain-Jang Li , Cheng-Chung Lin , Syun-Ming Jang
发明人： Lain-Jang Li , Cheng-Chung Lin , Syun-Ming Jang
IPC分类号： H01L2131
CPC分类号： H01L21/3146
摘要： Black diamond films, deposited using PECVD at low substrate temperatures, have been effectively stabilized by immersing them in de-ionized water at a temperature of about 90° C. for about 20 minutes or in a hydrogen peroxide solution (typically at a concentration of 10%) for about 60 minutes. Since it has been observed that the dielectric constant of the stabilized film increases with both immersion time and/or peroxide concentration, this effect may be used as a means for adjusting the dielectric constant of a black diamond film. Standard analytical techniques confirm that these low temperature stabilized films have electrical properties that are at least as good as those of films stabilized using high temperature heat treatments.
摘要翻译：通过在约90℃的温度下将它们浸入去离子水中约20分钟或在过氧化氢溶液中（通常浓度为10），已经有效地稳定了在低基材温度下使用PECVD沉积的黑色金刚石膜％）约60分钟。由于已经观察到稳定的膜的介电常数随着浸渍时间和/或过氧化物浓度的增加而增加，所以该效果可以用作调整黑色金刚石膜的介电常数的手段。标准分析技术证实这些低温稳定膜的电性能至少与使用高温热处理稳定的膜的电性能一样好。

2. 发明授权

US06407013B1 Soft plasma oxidizing plasma method for forming carbon doped silicon containing dielectric layer with enhanced adhesive properties 有权
标题翻译：软等离子体氧化等离子体法，用于形成具有增强的粘合性质的含碳掺杂的含硅介电层
公开(公告)号：US06407013B1
公开(公告)日：2002-06-18
申请号：US09761422
申请日：2001-01-16
申请人： Lain-Jong Li , Tien-I Bao , Cheng-Chung Lin , Syun-Ming Jang
发明人： Lain-Jong Li , Tien-I Bao , Cheng-Chung Lin , Syun-Ming Jang
IPC分类号： H01L2131
CPC分类号： H01L21/3105 , H01L21/76826 , H01L21/76829
摘要： Within a method for forming a dielectric layer within a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a carbon doped silicon containing dielectric layer. There is then treated the carbon doped silicon containing dielectric layer with an oxidizing plasma to form from the carbon doped silicon containing dielectric layer an oxidizing plasma treated carbon doped silicon containing dielectric layer. By treating the carbon doped silicon containing dielectric layer with the oxidizing plasma, particularly under mild conditions, to form therefrom the oxidizing plasma treated carbon doped silicon containing dielectric layer, adhesion of an additional microelectronic layer upon the oxidizing plasma treated carbon doped silicon containing dielectric layer is enhanced in comparison with adhesion of the additional microelectronic layer upon the carbon doped silicon containing dielectric layer, while not compromising dielectric properties of the carbon doped silicon containing dielectric layer.
摘要翻译：在微电子制造中形成电介质层的方法中，首先提供衬底。然后在衬底上形成含碳掺杂的含硅电介质层。然后用具有氧化等离子体的碳掺杂的含硅介电层处理从含碳掺杂的含硅介电层形成氧化等离子体处理的含碳的含硅介电层。通过用氧化等离子体处理含碳掺杂的含硅电介质层，特别是在温和条件下由其形成氧化等离子体处理的含碳硅的介电层，附加的微电子层与氧化等离子体处理的碳掺杂的含硅介电层与附加的微电子层对含碳的含硅介电层的粘附性相比增强，同时不损害含碳掺杂的含硅介电层的介电性质。

3. 发明授权

US09647066B2 Dummy FinFET structure and method of making same 有权
公开(公告)号：US09647066B2
公开(公告)日：2017-05-09
申请号：US13454960
申请日：2012-04-24
申请人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
发明人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
IPC分类号： H01L27/088 , H01L29/10 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/20
CPC分类号： H01L29/10 , H01L21/823431 , H01L27/0886 , H01L29/6681 , H01L29/785
摘要： A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.

4. 发明授权

US09269612B2 Mechanisms of forming damascene interconnect structures 有权
标题翻译：形成镶嵌互连结构的机制
公开(公告)号：US09269612B2
公开(公告)日：2016-02-23
申请号：US13434691
申请日：2012-03-29
申请人： Chien-An Chen , Wen-Jiun Liu , Chun-Chieh Lin , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
发明人： Chien-An Chen , Wen-Jiun Liu , Chun-Chieh Lin , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76819 , H01L21/76834 , H01L21/76843 , H01L21/76847 , H01L21/76849 , H01L21/7685 , H01L21/76864 , H01L21/76882 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.
摘要翻译：互连结构包括第一沟槽和第二沟槽。第二沟槽比第一沟槽宽。这两个沟槽都带有扩散阻挡层，并且第一导电层沉积在扩散阻挡层上。在第一导电层上沉积金属覆盖层。第二导电层沉积在第二沟槽中的金属覆盖层上。

5. 发明授权

US09029260B2 Gap filling method for dual damascene process 有权
标题翻译：双镶嵌工艺的间隙填充方法
公开(公告)号：US09029260B2
公开(公告)日：2015-05-12
申请号：US13161701
申请日：2011-06-16
申请人： Chun Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
发明人： Chun Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/44 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/7681 , H01L21/76831 , H01L21/76834 , H01L21/76846 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L29/511 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括形成具有多个第一开口的图案化电介质层。该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。该方法包括去除沟槽掩模层。

6. 发明授权

US08932962B2 Chemical dispensing system and method 有权
标题翻译：化学分配系统和方法
公开(公告)号：US08932962B2
公开(公告)日：2015-01-13
申请号：US13442040
申请日：2012-04-09
申请人： Weibo Yu , Kuo Bin Huang , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Kuo Bin Huang , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L21/302
CPC分类号： H01L21/6708 , H01L21/30608 , H01L21/31111 , H01L21/67109 , H01L22/12 , H01L22/20
摘要： A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer.
摘要翻译：用于将液体蚀刻剂分配到晶片上的方法和设备使用扫描分配喷嘴将液体蚀刻剂分配到晶片上，同时根据分配喷嘴在晶片上的径向位置实时控制蚀刻剂的分配温度。控制蚀刻剂的分配温度以提高蚀刻剂的有效性，从而补偿晶片中较低的蚀刻速率区域。

7. 发明授权

US08609484B2 Method for forming high-K metal gate device 有权
标题翻译：用于形成高K金属栅极器件的方法
公开(公告)号：US08609484B2
公开(公告)日：2013-12-17
申请号：US12617004
申请日：2009-11-12
申请人： Lee-Wee Tao , Han-Guan Chew , Harry Hak-Lay Chuang , Syun-Ming Jang
发明人： Lee-Wee Tao , Han-Guan Chew , Harry Hak-Lay Chuang , Syun-Ming Jang
IPC分类号： H01L29/00
CPC分类号： H01L29/7845 , H01L21/28518 , H01L21/3215 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成金属栅极，具有第一栅极电阻的金属栅极，去除金属栅极的一部分从而形成沟槽; 以及在所述沟槽内形成导电结构，使得所述导电结构的第二栅极电阻和所述金属栅极的剩余部分低于所述第一栅极电阻。

8. 发明申请

US20130157462A1 METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20130157462A1
公开(公告)日：2013-06-20
申请号：US13328680
申请日：2011-12-16
申请人： Chia Ying Lee , Chih-Yuan Ting , Jyu-Horng Shieh , Minghsing Tsai , Syun-Ming Jang
发明人： Chia Ying Lee , Chih-Yuan Ting , Jyu-Horng Shieh , Minghsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/28 , H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32
摘要： The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

9. 发明授权

US08330275B2 Interconnect structure for semiconductor devices 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US08330275B2
公开(公告)日：2012-12-11
申请号：US13290811
申请日：2011-11-07
申请人： Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
发明人： Hui-Lin Chang , Hung Chun Tsai , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L23/52
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L21/76889 , H01L23/528 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
摘要翻译：提供了形成在第一介电层中的铜互连结构的盖层。在一个实施例中，导电层位于电介质层内，并且导电层的顶表面具有凹陷，凸面或平面。合金层覆盖在导电层上，并且是具有来自导电层的第一材料和锗，砷，钨或镓的第二材料的硅化物合金。

10. 发明申请

US20120292767A1 Novel Approach for Reducing Copper Line Resistivity 有权
标题翻译：降低铜线电阻率的新方法
公开(公告)号：US20120292767A1
公开(公告)日：2012-11-22
申请号：US13561826
申请日：2012-07-30
申请人： Hsien-Ming Lee , Minghsing Tsai , Syun-Ming Jang
发明人： Hsien-Ming Lee , Minghsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L23/535
CPC分类号： H01L21/76856 , H01L21/76846 , H01L21/76849 , H01L21/76873
摘要： A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.
摘要翻译：提供一种用于制造集成电路结构的方法和所得到的集成电路结构。该方法包括形成低k电介质层; 在低k电介质层中形成开口; 形成覆盖所述低k电介质层的底部和侧壁的阻挡层; 在包括处理气体的环境中对阻挡层进行处理; 并用导电材料填充开口，其中导电材料在阻挡层上。

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