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1. 发明授权

US06407013B1 Soft plasma oxidizing plasma method for forming carbon doped silicon containing dielectric layer with enhanced adhesive properties 有权
标题翻译：软等离子体氧化等离子体法，用于形成具有增强的粘合性质的含碳掺杂的含硅介电层
公开(公告)号：US06407013B1
公开(公告)日：2002-06-18
申请号：US09761422
申请日：2001-01-16
申请人： Lain-Jong Li , Tien-I Bao , Cheng-Chung Lin , Syun-Ming Jang
发明人： Lain-Jong Li , Tien-I Bao , Cheng-Chung Lin , Syun-Ming Jang
IPC分类号： H01L2131
CPC分类号： H01L21/3105 , H01L21/76826 , H01L21/76829
摘要： Within a method for forming a dielectric layer within a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a carbon doped silicon containing dielectric layer. There is then treated the carbon doped silicon containing dielectric layer with an oxidizing plasma to form from the carbon doped silicon containing dielectric layer an oxidizing plasma treated carbon doped silicon containing dielectric layer. By treating the carbon doped silicon containing dielectric layer with the oxidizing plasma, particularly under mild conditions, to form therefrom the oxidizing plasma treated carbon doped silicon containing dielectric layer, adhesion of an additional microelectronic layer upon the oxidizing plasma treated carbon doped silicon containing dielectric layer is enhanced in comparison with adhesion of the additional microelectronic layer upon the carbon doped silicon containing dielectric layer, while not compromising dielectric properties of the carbon doped silicon containing dielectric layer.
摘要翻译：在微电子制造中形成电介质层的方法中，首先提供衬底。然后在衬底上形成含碳掺杂的含硅电介质层。然后用具有氧化等离子体的碳掺杂的含硅介电层处理从含碳掺杂的含硅介电层形成氧化等离子体处理的含碳的含硅介电层。通过用氧化等离子体处理含碳掺杂的含硅电介质层，特别是在温和条件下由其形成氧化等离子体处理的含碳硅的介电层，附加的微电子层与氧化等离子体处理的碳掺杂的含硅介电层与附加的微电子层对含碳的含硅介电层的粘附性相比增强，同时不损害含碳掺杂的含硅介电层的介电性质。

2. 发明授权

US06884659B2 Thin interface layer to improve copper etch stop 有权
标题翻译：薄界面层改善铜蚀刻停止
公开(公告)号：US06884659B2
公开(公告)日：2005-04-26
申请号：US10641648
申请日：2003-08-15
申请人： Bi-Trong Chen , Lain-Jong Li , Syun-Ming Jang , Shu E Ku , Tien I. Bao , Lih-Ping Li
发明人： Bi-Trong Chen , Lain-Jong Li , Syun-Ming Jang , Shu E Ku , Tien I. Bao , Lih-Ping Li
IPC分类号： C23C16/02 , H01L21/768 , H01L21/48 , B44C1/22
CPC分类号： C23C16/0272 , C23C16/0236 , H01L21/76832 , H01L21/76834 , H01L21/76838
摘要： In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.
摘要翻译：根据本发明的目的，提供了一种新的方法来提高沉积在铜层表面上的粘合强度。由于接口层之间的分子结合不良，常规的例如二氯硅烷（SiCl 2 H 2 H 2）或SiOC的蚀刻停止层与铜的下层具有差的粘合性。通过使用本发明提供的方法，铜的沉积层的表面可以提供特殊的增强界面层。这是铜层的预热，随后用氨（NH 3 3 N）和N 2 N 2进行预清洁处理，然后在铜上形成粘合增强层通过用烷基硅烷或烷基硅烷处理N 2或O 2或N 2 N 2层。

3. 发明授权

US07042049B2 Composite etching stop in semiconductor process integration 有权
标题翻译：复合蚀刻停止在半导体工艺集成
公开(公告)号：US07042049B2
公开(公告)日：2006-05-09
申请号：US10823149
申请日：2004-04-13
申请人： Lain-Jong Li , Tien-I Bao , Shwang-Ming Jeng , Syun-Ming Jang , Jun-Lung Huang , Jeng-Cheng Liu
发明人： Lain-Jong Li , Tien-I Bao , Shwang-Ming Jeng , Syun-Ming Jang , Jun-Lung Huang , Jeng-Cheng Liu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/76834
摘要： A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.
摘要翻译：描述形成复合蚀刻停止层的新方法。蚀刻停止层沉积在基板上，其中蚀刻停止层选自：碳化硅，氮化硅，SiCN，SiOC和SiOCN。通过覆盖在蚀刻停止层上的等离子体增强化学气相沉积来沉积TEOS氧化物层。复合蚀刻停止层具有改善的耐湿性，更好的蚀刻选择性和比其它蚀刻停止层更低的介电常数。

4. 发明授权

US06753260B1 Composite etching stop in semiconductor process integration 有权
公开(公告)号：US06753260B1
公开(公告)日：2004-06-22
申请号：US09970787
申请日：2001-10-05
申请人： Lain-Jong Li , Tien-I Bao , Shwang-Ming Jeng , Syun-Ming Jang , Jun-Lung Huang , Jeng-Cheng Liu
发明人： Lain-Jong Li , Tien-I Bao , Shwang-Ming Jeng , Syun-Ming Jang , Jun-Lung Huang , Jeng-Cheng Liu
IPC分类号： H01L21311
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/76834
摘要： A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.

5. 发明授权

US06623654B2 Thin interface layer to improve copper etch stop 有权
公开(公告)号：US06623654B2
公开(公告)日：2003-09-23
申请号：US10035578
申请日：2001-11-09
申请人： Bi-Trong Chen , Lain-Jong Li , Syun-Ming Jang , Shu E Ku , Tien I. Bao , Lih-Ping Li
发明人： Bi-Trong Chen , Lain-Jong Li , Syun-Ming Jang , Shu E Ku , Tien I. Bao , Lih-Ping Li
IPC分类号： B44C122
CPC分类号： C23C16/0272 , C23C16/0236 , H01L21/76832 , H01L21/76834 , H01L21/76838
摘要： In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.

6. 发明授权

US06878621B2 Method of fabricating barrierless and embedded copper damascene interconnects 失效
标题翻译：制造无障碍和嵌入铜大马士革互连的方法
公开(公告)号：US06878621B2
公开(公告)日：2005-04-12
申请号：US10346382
申请日：2003-01-17
申请人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76835 , H01L21/76885
摘要： A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.
摘要翻译：一种形成至少一个无障碍嵌入金属结构的方法，包括以下步骤。具有形成在其上的图案化电介质层的结构，其中至少一个开口暴露出结构的至少一个相应部分。在每个相应的开口内形成相应的金属结构。去除第一电介质层以暴露相应的至少一个金属结构的顶部和至少一部分侧壁。介电阻挡层形成在相应的金属结构的结构和暴露的顶部上。在电介质阻挡层上方形成第二个保形介电层，以完成嵌入在第二保形电介质层内的相应无障碍的至少一个金属结构。电介质阻挡层防止包含相应的至少一种金属结构的金属扩散到第二保形电介质层中。

7. 发明授权

US06908773B2 ATR-FTIR metal surface cleanliness monitoring 失效
标题翻译： ATR-FTIR金属表面清洁度监测
公开(公告)号：US06908773B2
公开(公告)日：2005-06-21
申请号：US10102574
申请日：2002-03-19
申请人： Lain-Jong Li , Syun-Ming Jang , Chung-Chi Ko
发明人： Lain-Jong Li , Syun-Ming Jang , Chung-Chi Ko
IPC分类号： G01N21/35 , G01N21/55 , G01R31/26 , H01L21/66
CPC分类号： G01N21/35 , G01N21/3563 , G01N21/552 , G01N21/94 , G01N2021/3595
摘要： Attenuated total reflectance (ATR)-Fourier transform infrared (FTIR) metal surface cleanliness monitoring is disclosed. A metal surface of a semiconductor die is impinged with an infrared (IR) beam, such as can be accomplished by using an ATR technique. The IR beam as reflected by the metal surface is measured. For instance, an interferogram of the reflected IR beam may be measured. A Fourier transform of the interferogram may also be performed, in accordance with an FTIR technique. To determine whether the metal surface is contaminated, the IR beam as reflected is compared to a reference sample. For example, the Fourier transform of the interferogram may be compared to the reference sample. If there is deviation by more than a threshold, the metal surface may be concluded as being contaminated.
摘要翻译：公开了衰减全反射（ATR） - 傅立叶变换红外（FTIR）金属表面清洁度监测。半导体管芯的金属表面被红外（IR）光束照射，例如可以通过使用ATR技术来实现。测量由金属表面反射的IR光束。例如，可以测量反射的IR光束的干涉图。干涉图的傅立叶变换也可以根据FTIR技术进行。为了确定金属表面是否被污染，将反射的IR光束与参考样品进行比较。例如，干涉图的傅立叶变换可以与参考样本进行比较。如果偏差大于阈值，金属表面可能被认定为被污染。

8. 发明授权

US06657284B1 Graded dielectric layer and method for fabrication thereof 有权
标题翻译：梯度介电层及其制造方法
公开(公告)号：US06657284B1
公开(公告)日：2003-12-02
申请号：US09727634
申请日：2000-12-01
申请人： Lain-Jong Li , Shwang-Ming Jeng , Syun-Ming Jang , Chen-Hua Yu
发明人： Lain-Jong Li , Shwang-Ming Jeng , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L2358
CPC分类号： H01L21/76822 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/31633 , H01L21/76801 , H01L21/76808 , H01L21/76813 , H01L23/5329 , H01L2221/1031 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Within a method for forming a dielectric layer, there is first provided a substrate. There is then formed over the substrate a dielectric layer, wherein the dielectric layer is formed from a dielectric material comprising silicon, carbon and nitrogen. Preferably, a nitrogen content is graded within a thickness of the dielectric layer to provide an upper lying nitrogen rich contiguous surface layer of the dielectric layer and a lower lying nitrogen poor contiguous layer of the dielectric layer. The method contemplates a microelectronic fabrication having formed therein a dielectric layer formed in accord with the method. The method provides the resulting dielectric layer with a lower dielectric constant and enhanced adhesion properties as a substrate layer.
摘要翻译：在形成电介质层的方法中，首先提供衬底。然后在衬底上形成介电层，其中介电层由包含硅，碳和氮的电介质材料形成。优选地，氮含量在介电层的厚度内分级，以提供电介质层的上位氮富连续表面层和电介质层的较低位置的氮不良连续层。该方法考虑了在其中形成有根据该方法形成的电介质层的微电子制造。该方法提供了所得到的介电层具有较低介电常数和增强的作为基底层的粘合性能。

9. 发明授权

US06319809B1 Method to reduce via poison in low-k Cu dual damascene by UV-treatment 有权
标题翻译：通过紫外线处理减少低k Cu双镶嵌物的通过毒物的方法
公开(公告)号：US06319809B1
公开(公告)日：2001-11-20
申请号：US09614595
申请日：2000-07-12
申请人： Weng Chang , Lain-Jong Li , Shwang Ming Jeng , Syun-Ming Jang
发明人： Weng Chang , Lain-Jong Li , Shwang Ming Jeng , Syun-Ming Jang
IPC分类号： H01L2144
CPC分类号： H01L21/76825 , H01L21/76807 , H01L21/76814
摘要： A method to reduce via poisoning in low-k copper dual damascene interconnects through ultraviolet (UV) irradiation of the damascene structure is disclosed. This is accomplished by irradiating the insulative layers each time the layers are etched to form a portion of the damascene structure. Thus, irradiation is performed once after the forming of a trench or a via, and again for the second time when the insulative layers are etched to form the remaining trench or via. The trench and hole openings of the dual damascene structure are exposed to UV light in a dry ozone environment, which then favorably alters the surface characteristics of the low-k dielectric walls which are normally hydrophobic. Hence, during etching, moisture is not absorbed into the walls. Furthermore, it is found that the UV treatment inhibits reaction between the walls and the photoresist used during the forming of the damascene structure, thereby providing clean openings without any photoresist residue, and hence, much less poisoned contacts/vias. Consequently, as copper is deposited into the clean damascene, voids are avoided, and a Cu dual damascene interconnect with low RC delay characteristics is obtained.
摘要翻译：公开了一种通过紫外（UV）照射大马士革结构来减少低k铜双镶嵌互连中的通孔中毒的方法。这是通过在每次蚀刻层以形成镶嵌结构的一部分时照射绝缘层来实现的。因此，在形成沟槽或通孔之后进行一次照射，并且再次在绝缘层被蚀刻以形成剩余的沟槽或通孔时再次进行。双重镶嵌结构的沟槽和孔洞在干燥臭氧环境中暴露于紫外线，这有利地改变通常是疏水性的低k电介质壁的表面特性。因此，在蚀刻期间，水分不会被吸收到壁中。此外，发现UV处理抑制在形成镶嵌结构期间使用的壁和光致抗蚀剂之间的反应，从而提供清洁的开口，而没有任何光致抗蚀剂残留物，因此，更少中毒的触点/通孔。因此，当铜沉积到清洁的镶嵌中时，避免了空隙，并且获得具有低RC延迟特性的铜双镶嵌互连。

10. 发明申请

US20060115980A1 Method for decreasing a dielectric constant of a low-k film 审中-公开
标题翻译：降低低k膜的介电常数的方法
公开(公告)号：US20060115980A1
公开(公告)日：2006-06-01
申请号：US11130044
申请日：2005-05-16
申请人： Chung-Chi Ko , Lih-Ping Li , Lain-Jong Li , Syun-Ming Jang
发明人： Chung-Chi Ko , Lih-Ping Li , Lain-Jong Li , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76835 , C23C16/401 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31633 , H01L21/76807 , H01L21/76834 , H01L21/76843
摘要： A method of forming a low dielectric constant film that can be used in a damascene process is disclosed. An organosilicon precursor such as octamethylcyclotrisiloxane (OMCTS) or any other compound that contains Si, C, and H and optionally O is transported into a PECVD chamber with a carrier gas such as CO or CO2 to provide a soft oxidation environment that leads to a higher carbon content and low k value in the deposited film. The carrier gas may replace helium or argon that have a higher bombardment property that can damage the substrate. Since CO and CO2 can contribute carbon to the deposited film, a lower k value is achieved than when an inert carrier gas is employed. The deposited film can be employed, for example, as a dielectric layer in a damascene stack or as an etch stop layer.
摘要翻译：公开了一种形成可用于镶嵌工艺中的低介电常数膜的方法。将诸如八甲基环三硅氧烷（OMCTS）的有机硅前体或含有Si，C和H以及任选的O的任何其它化合物转移到具有载体气体如CO或CO 2的PECVD室中，以提供软氧化环境导致沉积膜中碳含量较高，k值低。载气可以代替具有较高轰击性能的氦或氩，这可能损坏基底。由于CO和CO 2可以对沉积膜贡献碳，所以实现比使用惰性载气时更低的k值。沉积膜可以用作例如镶嵌层中的介电层或蚀刻停止层。

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