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1. 发明申请

US20140241028A1 TWO-BIT READ-ONLY MEMORY CELL 有权
标题翻译：两位只读存储器单元
公开(公告)号：US20140241028A1
公开(公告)日：2014-08-28
申请号：US13778258
申请日：2013-02-27
申请人： LSI CORPORATION
发明人： Rajiv Kumar Roy , Vikash
IPC分类号： G11C5/06
CPC分类号： G11C17/146 , G11C11/4097 , G11C11/5692
摘要： A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.
摘要翻译：只读存储器（ROM）单元具有串联在真位线和电压基准（例如，接地）之间的第一和第二晶体管，以及串联连接在补码位线和电压基准之间的第三和第四晶体管。第一和第三晶体管的栅极连接到第一字线，第二和第四晶体管的栅极连接到第二字线。 ROM单元被编程为通过适当地（i）将第一和第二晶体管之间的节点连接到真位线，补码位线或电压基准来存储两位信息的任何可能的组合，以及（ii）连接第三和第四晶体管之间的节点到真位线，补码位线或电压基准。

2. 发明申请

US20150302918A1 WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES 审中-公开
标题翻译：用于双轨静态随机存取存储器的字线解码器
公开(公告)号：US20150302918A1
公开(公告)日：2015-10-22
申请号：US14258236
申请日：2014-04-22
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Rasoju Veerabadra Chary , Dharmendra Kumar Rai , Rahul Sahu
IPC分类号： G11C11/418
CPC分类号： G11C11/418 , G11C8/08 , G11C11/413
摘要： Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path.
摘要翻译：公开了用于双轨SRAM器件的字线解码器用于高性能亚微米SRAM设计。一个实施例是一种SRAM器件，其包括存储单元阵列和穿过存储单元阵列的字线，用于选择存储单元阵列的存储单元。耦合到字线的行解码驱动器基于在外围电源的逻辑电平之间切换的选择信号来切换存储器单元电源的逻辑电平之间的字线。行解码器驱动器在字线访问路径下不使用电平移位器来切换字线。

3. 发明授权

US09064583B2 Fast access with low leakage and low power technique for read only memory devices 有权
标题翻译：以低泄漏和低功耗技术快速访问只读存储器件
公开(公告)号：US09064583B2
公开(公告)日：2015-06-23
申请号：US13775942
申请日：2013-02-25
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Disha Singh , Sahilpreet Singh
IPC分类号： G11C11/34 , G11C17/12
CPC分类号： G11C17/12
摘要： A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.
摘要翻译：一种只读存储器（ROM）和方法，用于提供较高的运行速度，减少泄漏，无核心单元备用泄漏和低功耗。 ROM单元（NMOS）的源极连接到虚拟接地线（VNGD）而不是VSS。因此，ROM单元可以可操作地耦合到位线，字线和虚拟地，其也用作列选择信号。 ROM的布置使得所选列的虚拟地被下拉到接地电压。未选择的列虚拟接地可以保持在电源电压，以确保不需要的列不会有任何子阈值电流（如Vds = 0）。由于在访问时间路径中不进行位线预充电，所以ROM实现了高的运行速度，同时减少了泄漏和低功耗。

4. 发明申请

US20150138863A1 INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES 审中-公开
标题翻译：用于分层位线SRAM架构的交互式写入协助
公开(公告)号：US20150138863A1
公开(公告)日：2015-05-21
申请号：US14086171
申请日：2013-11-21
申请人： LSI CORPORATION
发明人： Rajiv Kumar Roy , Donald Albert Evans , Rasoju Veerabadra Chary , Rahul Sahu
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/18
摘要： An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines.
摘要翻译： SRAM器件包括多个存储器单元和包括可操作以耦合到存储器单元的第一段的第一对位线的第一金属化层。该器件还包括第二金属化层，其包括可操作以耦合到存储器单元的第二段的第二对位线和与第一和第二金属化层交错的写辅助线，以提供与第一和第二金属层中的每一个基本上恒定的耦合电容和第二对位线。

5. 发明授权

US09177633B2 Bit line write assist for static random access memory architectures 有权
标题翻译：静态随机存取存储器架构的位线写入辅助
公开(公告)号：US09177633B2
公开(公告)日：2015-11-03
申请号：US14197552
申请日：2014-03-05
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Rasoju Veerabadra Chary , Rahul Sahu
IPC分类号： G11C11/00 , G11C11/4096 , G11C11/419 , G11C7/10 , G11C11/413 , G11C7/12
CPC分类号： G11C11/4096 , G11C7/1096 , G11C7/12 , G11C11/413 , G11C11/419
摘要： SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.
摘要翻译：公开了利用写辅助电路来改进位线的逻辑转换的SRAM器件。在一个实施例中，SRAM器件包括穿过用于将数据写入存储器单元的存储单元阵列的一对补充位线。位线具有第一端和第二端。一对补码写驱动器靠近写入位线的位线的第一端。写辅助电路接近位线的第二端，其接收预充电信号以辅助写驱动器将位线从逻辑零状态转换到逻辑1状态。写辅助电路还接收升压信号以帮助写驱动器将位线从逻辑1状态转换到逻辑零状态。

6. 发明申请

US20150255148A1 BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES 有权
标题翻译：用于静态随机访问存储器架构的位线写入辅助
公开(公告)号：US20150255148A1
公开(公告)日：2015-09-10
申请号：US14197552
申请日：2014-03-05
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Rasoju Veerabadra Chary , Rahul Sahu
IPC分类号： G11C11/4096
CPC分类号： G11C11/4096 , G11C7/1096 , G11C7/12 , G11C11/413 , G11C11/419
摘要： SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.
摘要翻译：公开了利用写辅助电路来改进位线的逻辑转换的SRAM器件。在一个实施例中，SRAM器件包括穿过用于将数据写入存储器单元的存储单元阵列的一对补充位线。位线具有第一端和第二端。一对补码写驱动器靠近写入位线的位线的第一端。写辅助电路接近位线的第二端，其接收预充电信号以辅助写驱动器将位线从逻辑零状态转换到逻辑1状态。写辅助电路还接收升压信号以帮助写驱动器将位线从逻辑1状态转换到逻辑零状态。

7. 发明授权

US09111637B1 Differential latch word line assist for SRAM 有权
标题翻译： SRAM的差分锁存字线协助
公开(公告)号：US09111637B1
公开(公告)日：2015-08-18
申请号：US14274965
申请日：2014-05-12
申请人： LSI Corporation
发明人： Rahul Sahu , Rajiv Kumar Roy , Rasoju Veerabadra Chary , Dharmendra Kumar Rai
IPC分类号： G11C11/00 , G11C11/417 , G11C5/06
CPC分类号： G11C11/417 , G11C8/08 , G11C8/16 , G11C11/418
摘要： Word line assist circuits are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a pair of word lines that traverse the memory cell array for selecting memory cells. The SRAM device further includes a pair of word line drivers, each coupled to one of the word lines. The SRAM device further includes a word line assist circuit coupled to the pair of word lines that receives an enable signal. Responsive to receiving the enable signal, the word line assist circuit assists the first word line driver and the second word line driver in transitioning their respective word lines from a logic level zero to a logic level one in response to a voltage differential between the word lines.
摘要翻译：公开了用于高性能亚微米SRAM设计的字线辅助电路。一个实施例是一种SRAM器件，其包括存储单元阵列和穿过存储单元阵列的一对字线，用于选择存储单元。 SRAM器件还包括一对字线驱动器，每个字线驱动器耦合到一条字线。该SRAM器件还包括一个字线辅助电路，它耦合到一对接收使能信号的字线。响应于接收使能信号，字线辅助电路协助第一字线驱动器和第二字线驱动器响应于字线之间的电压差将它们各自的字线从逻辑电平0转换到逻辑电平1 。

8. 发明授权

US09177635B1 Dual rail single-ended read data paths for static random access memories 有权
标题翻译：用于静态随机存取存储器的双轨单端读取数据路径
公开(公告)号：US09177635B1
公开(公告)日：2015-11-03
申请号：US14259994
申请日：2014-04-23
申请人： LSI Corporation
发明人： Donald Albert Evans , Rasoju Veerabadra Chary , Rajiv Kumar Roy , Rahul Sahu
IPC分类号： G11C11/00 , G11C11/419 , G11C5/06
CPC分类号： G11C11/419 , G11C5/063
摘要： Single-ended read circuits for SRAM devices are disclosed for high performance sub-micron designs. One embodiment is an SRAM device that includes a memory cell array and a bit line traversing the memory cell array for reading data from memory cells of the memory cell array. A read circuit coupled to the bit line translates data stored in a memory cell from a cell voltage of the memory cells to a peripheral voltage of an output of the SRAM device while bypassing a level shifter in the read data path.
摘要翻译：公开了用于SRAM器件的单端读取电路用于高性能亚微米设计。一个实施例是一种SRAM器件，其包括存储单元阵列和穿过存储单元阵列的位线，用于从存储单元阵列的存储单元读取数据。耦合到位线的读取电路将存储单元中存储的数据从存储器单元的单元电压转换为SRAM器件的输出的外围电压，同时绕过读取数据路径中的电平移位器。

9. 发明授权

US09147495B2 Two-bit read-only memory cell 有权
标题翻译：两位只读存储单元
公开(公告)号：US09147495B2
公开(公告)日：2015-09-29
申请号：US13778258
申请日：2013-02-27
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Vikash
IPC分类号： G11C11/4097 , G11C17/14 , G11C11/56
CPC分类号： G11C17/146 , G11C11/4097 , G11C11/5692
摘要： A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.
摘要翻译：只读存储器（ROM）单元具有串联在真位线和电压基准（例如，接地）之间的第一和第二晶体管，以及串联连接在补码位线和电压基准之间的第三和第四晶体管。第一和第三晶体管的栅极连接到第一字线，第二和第四晶体管的栅极连接到第二字线。 ROM单元被编程为通过适当地（i）将第一和第二晶体管之间的节点连接到真位线，补码位线或电压基准来存储两位信息的任何可能的组合，以及（ii）连接第三和第四晶体管之间的节点到真位线，补码位线或电压基准。

10. 发明申请

US20150138876A1 GLOBAL BITLINE WRITE ASSIST FOR SRAM ARCHITECTURES 审中-公开
标题翻译：用于SRAM架构的全球双引号写入协助
公开(公告)号：US20150138876A1
公开(公告)日：2015-05-21
申请号：US14153560
申请日：2014-01-13
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Rasoju Veerabadra Chary
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/18 , G11C11/418
摘要： An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment.
摘要翻译： SRAM器件包括具有多个存储器单元的分段存储单元阵列。存储器单元的每个段包括耦合到段中的存储器单元的位线。 SRAM器件还包括遍历分段存储单元阵列的全局位线，并且经由本地位线通信地耦合到存储器单元段以写入存储单元。 SRAM器件还包括全局输入/输出模块，可操作以将全局位线保持在逻辑0，以便在要写入数据时将全局位线切换为逻辑位线，以在全局位置之后选择存储器单元的一段以进行写入位线被切换，并且当数据被写入所选择的存储器单元段以将全局位线切换到逻辑0以向所选存储器单元段的本地位线提供负升压电压时。

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