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1. 发明授权

US06728140B2 Threshold voltage convergence 有权
标题翻译：门限电压收敛
公开(公告)号：US06728140B2
公开(公告)日：2004-04-27
申请号：US10011157
申请日：2001-12-05
申请人： Kyung Joon Han , Joo Weon Park , Gyu-Wan Kwon , Dung Tran , Steve K. Hsia , Jong Seuk Lee , Dae Hyun Kim
发明人： Kyung Joon Han , Joo Weon Park , Gyu-Wan Kwon , Dung Tran , Steve K. Hsia , Jong Seuk Lee , Dae Hyun Kim
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.
摘要翻译：收敛信号包括用于在一个或多个快闪EEPROM存储单元（晶体管）中执行收敛过程的一系列电压脉冲。在一种情况下，会聚信号中的后续电压脉冲各自具有比先前脉冲更高的电压。在另一种情况下，会聚信号中的后续电压脉冲各自具有比先前脉冲更长的持续时间。集成电路包括存储单元的阵列和控制将收敛信号应用于一个或多个存储器单元的擦除控制单元。集成电路可以是使用批量，扇区或页面模式擦除的串行或并行闪存EEPROM。

2. 发明授权

US06873004B1 Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof 有权
标题翻译：虚拟接地单晶体管存储单元，并入其的存储器阵列及其操作方法
公开(公告)号：US06873004B1
公开(公告)日：2005-03-29
申请号：US10358645
申请日：2003-02-04
申请人： Kyung Joon Han , Steve K. Hsia , Joo Weon Park , Gyu-Wan Kwon , Jong Seuk Lee
发明人： Kyung Joon Han , Steve K. Hsia , Joo Weon Park , Gyu-Wan Kwon , Jong Seuk Lee
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/66825 , H01L29/7885
摘要： An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.
摘要翻译：不对称的虚拟接地单晶体管浮动栅极存储单元具有覆盖p阱中的沟道区的浮置栅极，位于重掺杂n +漏极区和轻掺杂n-源区之间的沟道区。称为“卤素”的重掺杂p +区被设置在与重掺杂n +漏极相邻的沟道中。浮栅通过通常薄的隧道氧化物与沟道区间隔开。具有渐变源/沟道结的轻掺杂源减少源侧CHE生成。在一个变型中，源极和浮置栅极之间的较厚的氧化物减少了源极侧的CHE注入。在与漏极相邻的沟道中具有卤素注入的重掺杂漏极增强漏侧CHE生成。

3. 发明授权

US06826080B2 Virtual ground nonvolatile semiconductor memory array architecture and integrated circuit structure therefor 有权
标题翻译：虚拟地非易失性半导体存储器阵列结构及其集成电路结构
公开(公告)号：US06826080B2
公开(公告)日：2004-11-30
申请号：US10154979
申请日：2002-05-24
申请人： Joo Weon Park , Kyung Joon Han , Gyu-Wan Kwon , Jong Seuk Lee
发明人： Joo Weon Park , Kyung Joon Han , Gyu-Wan Kwon , Jong Seuk Lee
IPC分类号： G11C1604
CPC分类号： G11C16/0491 , G11C16/08
摘要： In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.
摘要翻译：在非易失性存储单元阵列中，每个扇区的存储单元被组织成连续单元组，这些组优选地具有相同的尺寸，并且优选地通过适当的隔离结构（例如场电介质）在行和列方向上彼此隔离或沟槽电介质。由于单元组隔离，每组列线可以通过其自己的相对较小的程序列选择进行解码，优选地以所有列列组为基本相同的形式复制。虽然每个节目列选择优选地用于解码一组列线，但是如果需要解码两组或更多组列线，则可以使用较大的节目列选择。读列选择可以根据需要对一行或多组列线进行解码。解码的列线的数量可以与解码的列线的数量相同或不同。

4. 发明授权

US06909639B2 Nonvolatile memory having bit line discharge, and method of operation thereof 有权
标题翻译：具有位线放电的非易失性存储器及其操作方法
公开(公告)号：US06909639B2
公开(公告)日：2005-06-21
申请号：US10421458
申请日：2003-04-22
申请人： Joo Weon Park , Poongyeub Lee , Eungjoon Park , Kyung Joon Han
发明人： Joo Weon Park , Poongyeub Lee , Eungjoon Park , Kyung Joon Han
IPC分类号： G11C11/34 , G11C16/00 , G11C16/04 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , G11C16/10 , H01L27/115 , H01L29/7885
摘要： The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim (“FN”) tunneling, highly conductive and lengthy bit lines, buried and relatively short sub-bit lines and a programming discharge circuit for controlling spurious voltages on the bit lines that can arise when some of the bit lines are left floating during programming. Discharge control transistor respectively coupled to the bit lines direct current into a discharge section. A discharge section may be provided for each bit line, or shared by all bit lines. The discharge section may be a fixed circuit section for use through the programming process or may be selected from multiple discharge options.
摘要翻译：通过在编程期间放电非易失性存储器阵列的浮置位线来减少位干扰的问题。示例性虚拟接地存储器阵列使用使用Fowler-Nordheim（“FN”）隧道，高导电性和长度位线，埋入和相对短的子位线以及用于控制的编程放电电路来编程的单晶体管浮栅型存储器单元当编程中某些位线悬空时，位线上的杂散电压可能会出现。分别与位线耦合的放电控制晶体管将电流引入放电部分。可以为每个位线提供放电部分，或者由所有位线共享放电部分。放电部分可以是通过编程处理使用的固定电路部分，或者可以从多个放电选项中选择。

5. 发明授权

US06747899B2 Method and apparatus for multiple byte or page mode programming of a flash memory array 有权
公开(公告)号：US06747899B2
公开(公告)日：2004-06-08
申请号：US10035414
申请日：2001-11-08
申请人： Steve K. Hsia , Kyung Joon Han , Dung Tran
发明人： Steve K. Hsia , Kyung Joon Han , Dung Tran
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C8/08 , G11C16/08 , G11C16/10 , G11C2216/14
摘要： A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

6. 发明授权

US06731544B2 Method and apparatus for multiple byte or page mode programming of a flash memory array 有权
标题翻译：用于闪存阵列的多字节或页面模式编程的方法和装置
公开(公告)号：US06731544B2
公开(公告)日：2004-05-04
申请号：US10039518
申请日：2001-11-08
申请人： Kyung Joon Han , Dung Tran , Steven W. Longcor , Steve K. Hsia
发明人： Kyung Joon Han , Dung Tran , Steven W. Longcor , Steve K. Hsia
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C16/10 , G11C16/3418
摘要： A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.
摘要翻译：存储器阵列包含使用Fowler-Nordheim（“FN”）在通道区域进行隧道扫描的存储单元，并使用通道热电子注入（“CHE”）或通道引发的二次电子注入（“CISEI”）进行编程，。为了在编程操作和读取操作期间减少未选择存储单元的浮动栅极电位的干扰，未选择的字线被带到负电位而不是地电位。为了减少FN擦除操作期间未选择的存储单元的浮动栅极电势的干扰，未选择的字线被带到正电位而不是地电位。

7. 发明授权

US07362610B1 Programming method for non-volatile memory and non-volatile memory-based programmable logic device 有权
标题翻译：非易失性存储器和非易失性存储器可编程逻辑器件的编程方法
公开(公告)号：US07362610B1
公开(公告)日：2008-04-22
申请号：US11319751
申请日：2005-12-27
申请人： Robert M. Salter, III , Kyung Joon Han , Sung-Rae Kim , Nigel Chan
发明人： Robert M. Salter, III , Kyung Joon Han , Sung-Rae Kim , Nigel Chan
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.
摘要翻译：一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。在编程段期间，每个编程段中的编程电位增加。连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

8. 发明授权

US6072720A Nonvolatile reprogrammable interconnect cell with programmable buried bitline 有权
标题翻译：具有可编程掩埋位线的非易失性可编程互连单元
公开(公告)号：US6072720A
公开(公告)日：2000-06-06
申请号：US205876
申请日：1998-12-04
申请人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
发明人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
IPC分类号： G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/11524
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.
摘要翻译：公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。单元的编程通过与开关晶体管和感测晶体管并置的埋入位线来实现，开关晶体管和浮动栅极和控制栅极在其上。感测晶体管可以与开关晶体管的制造同时制造，由此两个晶体管的掺杂剂浓度相同。

9. 发明授权

US5838040A Nonvolatile reprogrammable interconnect cell with FN tunneling in sense 失效
标题翻译：具有FN隧道效应的非易失性可编程互连单元
公开(公告)号：US5838040A
公开(公告)日：1998-11-17
申请号：US829374
申请日：1997-03-31
申请人： Robert M. Salter, III , Kyung Joon Han , Jack Zezhong Peng , Victor Levchenko , Robert V. Broze
发明人： Robert M. Salter, III , Kyung Joon Han , Jack Zezhong Peng , Victor Levchenko , Robert V. Broze
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/82 , H01L27/115 , H01L29/788 , H01L29/792 , H03K19/173
CPC分类号： G11C16/0441 , H01L27/115
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.
摘要翻译：公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是公共的，并且控制栅极是共同的。通过对公共控制栅极线和感测晶体管的源极/漏极的电压偏置来实现单元的编程。

10. 发明授权

US09178389B2 Wireless power transmission system and method of controlling the same 有权
标题翻译：无线电力传输系统及其控制方法
公开(公告)号：US09178389B2
公开(公告)日：2015-11-03
申请号：US13569098
申请日：2012-08-07
申请人： Sang Hoon Hwang , Kyung Joon Han , Tah Joon Park
发明人： Sang Hoon Hwang , Kyung Joon Han , Tah Joon Park
IPC分类号： H02J7/00 , H02J17/00
CPC分类号： H02J7/025 , H02J5/005 , H02J17/00 , H02J50/12 , H02J50/80
摘要： Disclosed herein is a wireless power transmission system, including: a transmission unit generating and transmitting power for charging a battery; a reception unit receiving the transmitted power and charging the battery with power; and a transmission control unit detecting a charging status of the battery by using the transmitted power, and, if the charging status of the battery is in a damage section due to reflective power, controlling the transmission unit to transmit power lower than power of a normal operation, whereby damage of transmission and reception devices due to a reflective wave can be minimized.
摘要翻译：这里公开了一种无线电力传输系统，包括：传输单元，其产生和发送用于对电池充电的电力; 接收发送的电力的接收单元，并且对电池充电; 以及发送控制单元，通过使用发送功率来检测电池的充电状态，并且如果电池的充电状态由于反射功率而处于损坏部分，则控制发送单元发送低于正常功率的功率可以使反射波引起的发送接收装置的损坏最小化。

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