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1. 发明授权

US06909639B2 Nonvolatile memory having bit line discharge, and method of operation thereof 有权
标题翻译：具有位线放电的非易失性存储器及其操作方法
公开(公告)号：US06909639B2
公开(公告)日：2005-06-21
申请号：US10421458
申请日：2003-04-22
申请人： Joo Weon Park , Poongyeub Lee , Eungjoon Park , Kyung Joon Han
发明人： Joo Weon Park , Poongyeub Lee , Eungjoon Park , Kyung Joon Han
IPC分类号： G11C11/34 , G11C16/00 , G11C16/04 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , G11C16/10 , H01L27/115 , H01L29/7885
摘要： The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim (“FN”) tunneling, highly conductive and lengthy bit lines, buried and relatively short sub-bit lines and a programming discharge circuit for controlling spurious voltages on the bit lines that can arise when some of the bit lines are left floating during programming. Discharge control transistor respectively coupled to the bit lines direct current into a discharge section. A discharge section may be provided for each bit line, or shared by all bit lines. The discharge section may be a fixed circuit section for use through the programming process or may be selected from multiple discharge options.
摘要翻译：通过在编程期间放电非易失性存储器阵列的浮置位线来减少位干扰的问题。示例性虚拟接地存储器阵列使用使用Fowler-Nordheim（“FN”）隧道，高导电性和长度位线，埋入和相对短的子位线以及用于控制的编程放电电路来编程的单晶体管浮栅型存储器单元当编程中某些位线悬空时，位线上的杂散电压可能会出现。分别与位线耦合的放电控制晶体管将电流引入放电部分。可以为每个位线提供放电部分，或者由所有位线共享放电部分。放电部分可以是通过编程处理使用的固定电路部分，或者可以从多个放电选项中选择。

2. 发明授权

US06768671B1 Nonvolatile memory and method of operation thereof to control erase disturb 有权
标题翻译：非易失性存储器及其操作方法来控制擦除干扰
公开(公告)号：US06768671B1
公开(公告)日：2004-07-27
申请号：US10382719
申请日：2003-03-05
申请人： Poongyeub Lee , Joo Weon Park , Kwangho Kim , Eungjoon Park
发明人： Poongyeub Lee , Joo Weon Park , Kwangho Kim , Eungjoon Park
IPC分类号： G11C1616
CPC分类号： G11C16/08 , G11C16/12 , G11C16/3418
摘要： In an array of nonvolatile memory cells, as many memory cells as desired and indeed even the entire array of memory cells may be placed in a single region of the bulk, illustratively a p-well. Peripheral circuitry is used to in effect section the memory array into blocks and groups of blocks, and to establish suitable biasing and counter-biasing within those blocks and groups during page or block erase operations to limit erase disturb. Each group is provided with its own set of voltage switches, which furnishes the bias voltages for the various modes of operation, including erase. Each of the voltage switches furnish either a large positive voltage when its group is selected, or a large negative voltage when its group is unselected. The size of the group is established as a compromise between degree of erase disturb and substrate area required for the voltage switches.
摘要翻译：在非易失性存储器单元的阵列中，根据需要，甚至整个存储单元阵列可以将多个存储器单元放置在大块的单个区域中，示例性地为p阱。外设电路用于将存储器阵列有效地划分为块和块组，并且在页或块擦除操作期间在这些块和组内建立合适的偏置和反偏置以限制擦除干扰。每个组都有自己的一组电压开关，它们为各种工作模式（包括擦除）提供偏置电压。每个电压开关在选择组时提供大的正电压，或者当其组被选择时提供大的负电压。该组的尺寸被确定为电压开关所需的擦除干扰程度和衬底面积之间的折衷。

3. 发明申请

US20100049948A1 Serial flash semiconductor memory 审中-公开
标题翻译：串行闪存半导体存储器
公开(公告)号：US20100049948A1
公开(公告)日：2010-02-25
申请号：US12459590
申请日：2009-07-02
申请人： Robin J. Jigour , Eungjoon Park , Joo Weon Park , Jong Seuk Lee
发明人： Robin J. Jigour , Eungjoon Park , Joo Weon Park , Jong Seuk Lee
IPC分类号： G06F9/30 , G06F12/00 , G06F12/02
CPC分类号： G11C7/1045 , G11C8/04 , G11C16/26 , G11C2207/108 , G11C2216/30
摘要： A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.
摘要翻译：串行闪存具有多个可配置引脚，其中至少一个可选择性地配置用于单位串行数据传输或多位串行数据传输。在单位串行模式下，数据传输通过引脚逐位传输。在多位串行模式下，通过各个引脚一次传输多个连续位。串行闪存可能具有16个或更少的引脚，甚至8个或更少的引脚，因此可以使用低引脚数封装，例如8引脚或16引脚SOIC封装和8接点MLP / QFN / SON封装。单位串行类型协议的可用性支持与许多现有系统的兼容性，而多位串行类型协议的可用性使得串行闪存能够在可以支持它们的系统中提供数据传输速率显着快于标准串行闪存的可用性。

4. 发明授权

US07558900B2 Serial flash semiconductor memory 有权
标题翻译：串行闪存半导体存储器
公开(公告)号：US07558900B2
公开(公告)日：2009-07-07
申请号：US11078205
申请日：2005-03-11
申请人： Robin J. Jigour , Eungjoon Park , Joo Weon Park , Jong Seuk Lee
发明人： Robin J. Jigour , Eungjoon Park , Joo Weon Park , Jong Seuk Lee
IPC分类号： G06F13/14 , G06F3/00 , G06F13/42
CPC分类号： G11C7/1045 , G11C8/04 , G11C16/26 , G11C2207/108 , G11C2216/30
摘要： A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.
摘要翻译：串行闪存具有多个可配置引脚，其中至少一个可选择性地配置用于单位串行数据传输或多位串行数据传输。在单位串行模式下，数据传输通过引脚逐位传输。在多位串行模式下，通过各个引脚一次传输多个连续位。串行闪存可能具有16个或更少的引脚，甚至8个或更少的引脚，因此可以使用低引脚数封装，例如8引脚或16引脚SOIC封装和8接点MLP / QFN / SON封装。单位串行类型协议的可用性支持与许多现有系统的兼容性，而多位串行类型协议的可用性使得串行闪存能够在可以支持它们的系统中提供数据传输速率显着快于标准串行闪存的可用性。

5. 发明申请

US20060067123A1 Serial flash semiconductor memory 有权
公开(公告)号：US20060067123A1
公开(公告)日：2006-03-30
申请号：US11078205
申请日：2005-03-11
申请人： Robin Jigour , Eungjoon Park , Joo Park , Jong Lee
发明人： Robin Jigour , Eungjoon Park , Joo Park , Jong Lee
IPC分类号： G11C5/06 , G11C11/34 , G11C16/04
CPC分类号： G11C7/1045 , G11C8/04 , G11C16/26 , G11C2207/108 , G11C2216/30
摘要： A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

6. 发明授权

US06487125B2 Integrated circuit having an EEPROM and flash EPROM 有权
公开(公告)号：US06487125B2
公开(公告)日：2002-11-26
申请号：US10099291
申请日：2002-03-12
申请人： Eungjoon Park , Ali Pourkeramati
发明人： Eungjoon Park , Ali Pourkeramati
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , G11C16/0408
摘要： In accordance with the present invention, a non-volatile integrated circuit memory includes an EEPROM array comprising a plurality of memory cells and a flash EPROM array comprising a second plurality of memory cells, wherein the EEPROM array is capable of being erased byte-by-byte or word-by-word, and the flash EPROM array is capable of being erased sector-by-sector. Both arrays are formed using the same memory cell which is programmed using hot-electron injection and is erased using Fowler-Nordheim tunneling.

7. 发明授权

US06487113B1 Programming a phase-change memory with slow quench time 有权
标题翻译：编程具有缓慢淬火时间的相变存储器
公开(公告)号：US06487113B1
公开(公告)日：2002-11-26
申请号：US09895054
申请日：2001-06-29
申请人： Eungjoon Park , Tyler A. Lowrey
发明人： Eungjoon Park , Tyler A. Lowrey
IPC分类号： G11C1100
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0038 , G11C2013/0078 , G11C2013/0092
摘要： A memory array is operated by increasing a number of currents through a number of corresponding cells of the array, where each cell has a structural phase-change material to store data for that cell. Each of the currents are increased to an upper level that is sufficiently high that can cause the corresponding cell to be in a first state. Some of the currents are decreased to lower levels at sufficiently high rates that cause their corresponding cells to be programmed to the first state, while others are decreased at sufficiently low rates that cause their corresponding cells to be programmed to a second state.
摘要翻译：存储器阵列通过增加穿过阵列的多个相应单元的数量的电流来操作，其中每个单元具有用于存储该单元的数据的结构相变材料。每个电流增加到足够高的上层，这可以使相应的单元处于第一状态。一些电流以足够高的速率降低到较低的水平，使得它们相应的单元被编程到第一状态，而其它电流以足够低的速率降低，使得它们的相应单元被编程到第二状态。

8. 发明授权

US6064251A System and method for a low voltage charge pump with large output voltage range 失效
标题翻译：具有大输出电压范围的低压电荷泵的系统和方法
公开(公告)号：US6064251A
公开(公告)日：2000-05-16
申请号：US920613
申请日：1997-08-27
申请人： Eungjoon Park
发明人： Eungjoon Park
IPC分类号： H02M3/07 , H03K3/00
CPC分类号： H02M3/073
摘要： A low voltage charge pump system with a large output voltage range is described. The charge pump system comprises eight charge pump stages, an output stage, and a four phase clock generator. The clock generator generates two sets of four phase shifted signals. The first set of four clock signals are coupled to the first four charge pump stages and have a logic high level of VCC. The second set of clock signals are coupled to the second four charge pump stages and have a logic high level of 2 VCC. Due to the body effect, the negative voltages at the charge pump output stages increases the threshold voltage of a pass transistor which couples the input and output in each charge pump. The larger high voltage level of the second set of clock signals enables the signals to overcome the body effect increased threshold voltages of the pass transistors. The pass transistors are then used to couple negative charge to the next charge pump stage, and positive charge to the preceding charge pump stage. The present invention charge pump system can thereby provide a large negative voltage output using a low power supply voltage. In the charge pump stages that receive the higher clock levels and in the output stage, the well of capacitor configured PMOS transistors that are coupled to the stage clock terminals is coupled to the source and drain of the transistors. Coupling the source, drain and well together prevents the 2 VCC voltage high level clock signals from forward biasing the p-n junction formed by the source and drain with the well. The charge pump stages and the output stage also include a p-n junction diode coupled from the output of the stage to ground.
摘要翻译：描述了具有大输出电压范围的低压电荷泵系统。电荷泵系统包括八个电荷泵级，输出级和四相时钟发生器。时钟发生器产生两组四个相移信号。第一组四个时钟信号耦合到前四个电荷泵级，并具有逻辑高电平的VCC。第二组时钟信号耦合到第二个四个电荷泵级，并具有2 VCC的逻辑高电平。由于身体效应，电荷泵输出级的负电压增加了耦合每个电荷泵中的输入和输出的通过晶体管的阈值电压。第二组时钟信号的较高的高电压电平使得信号能够克服通过晶体管增加的阈值电压的体效应。然后通过晶体管将负电荷耦合到下一个电荷泵级，并将正电荷耦合到前一电荷泵级。因此，本发明的电荷泵系统可以使用低电源电压提供大的负电压输出。在接收较高时钟电平且在输出级的电荷泵级中，耦合到级时钟端子的电容器配置的PMOS晶体管的阱耦合到晶体管的源极和漏极。耦合源极，漏极和阱一起防止2 VCC电压高电平时钟信号从源极和漏极与阱形成的p-n结正向偏置。电荷泵级和输出级还包括从级的输出端耦合到地的p-n结二极管。

9. 发明授权

US5999479A Row decoder for nonvolatile memory having a low-voltage power supply 失效
标题翻译：具有低压电源的非易失性存储器的行解码器
公开(公告)号：US5999479A
公开(公告)日：1999-12-07
申请号：US10202
申请日：1998-01-21
申请人： Eungjoon Park , Hsi-Hsien Hung
发明人： Eungjoon Park , Hsi-Hsien Hung
IPC分类号： G11C8/10 , G11C16/08 , G11C8/00
CPC分类号： G11C8/10 , G11C16/08
摘要： A row decoder for a nonvolatile memory having a low-voltage power supply that minimizes the load capacitance presented to a high voltage source without requiring additional circuitry. The row decoder accomplishes this by providing a local decoder having only one input requiring a boosted voltage higher than the power supply voltage. Further, predecoders are used to reduce the number of local decoders that receive the boosted voltage.
摘要翻译：一种用于具有低电压电源的非易失性存储器的行解码器，其将呈现给高电压源的负载电容最小化，而不需要额外的电路。行解码器通过提供仅需要一个高于电源电压的升高电压的输入的本地解码器来实现这一点。此外，预解码器用于减少接收升压电压的本地解码器的数量。

10. 发明授权

US07502267B2 Clock frequency doubler method and apparatus for serial flash testing 有权
标题翻译：用于串行闪存测试的时钟倍频器方法和装置
公开(公告)号：US07502267B2
公开(公告)日：2009-03-10
申请号：US11526124
申请日：2006-09-22
申请人： Tien-Ler Lin , Kwangho Kim , Hui Chen , Eungjoon Park
发明人： Tien-Ler Lin , Kwangho Kim , Hui Chen , Eungjoon Park
IPC分类号： G11C7/00 , G11C11/34 , G11C8/00
CPC分类号： G11C29/14 , G11C7/22 , G11C7/222 , G11C29/12015
摘要： Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.
摘要翻译：用于以比由存储器测试器提供的时钟速率更高的时钟速率测试存储器件的方法和装置。该方法包括提供能够产生以第一时钟频率为特征的第一时钟信号并将第一时钟信号施加到存储器件的存储器测试器。该方法还包括接收用于激活高时钟频率测试模式的命令。该方法响应于第一时钟信号在存储器件中产生第二时钟信号。第二时钟信号的特征在于高于第一时钟频率的第二时钟频率。然后该方法以第二个时钟频率测试存储器件。在具体实施例中，该方法被应用于串行闪存设备。本发明还可以应用于测试和操作包括同步电路的其它存储器件或系统。

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