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1. 发明授权

US6072720A Nonvolatile reprogrammable interconnect cell with programmable buried bitline 有权
标题翻译：具有可编程掩埋位线的非易失性可编程互连单元
公开(公告)号：US6072720A
公开(公告)日：2000-06-06
申请号：US205876
申请日：1998-12-04
申请人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
发明人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
IPC分类号： G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/11524
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.
摘要翻译：公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。单元的编程通过与开关晶体管和感测晶体管并置的埋入位线来实现，开关晶体管和浮动栅极和控制栅极在其上。感测晶体管可以与开关晶体管的制造同时制造，由此两个晶体管的掺杂剂浓度相同。

2. 发明授权

US6137728A Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor 有权
标题翻译：非易失性可重新编程的互连单元，具有可编程的埋入式源/漏极，在感应晶体管中
公开(公告)号：US6137728A
公开(公告)日：2000-10-24
申请号：US205678
申请日：1998-12-04
申请人： Jack Zezhong Peng , Volker Hecht , Robert M. Salter, III , Kyung Joon Han , Robert U. Broze
发明人： Jack Zezhong Peng , Volker Hecht , Robert M. Salter, III , Kyung Joon Han , Robert U. Broze
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11803 , G11C16/0441 , H01L27/115
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.
摘要翻译：公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。通过对公共控制栅极线和感测晶体管的源极/漏极的电压偏置来实现单元的编程。感测场效应晶体管的源极/漏极由在形成多晶硅浮置栅极和控制栅极之前形成的掩埋掺杂层（例如P掺杂衬底中的N +）形成。掺杂剂从掩埋源/漏极到浮置栅极下方的沟道的横向扩散有助于在擦除和编程操作期间的电子隧穿，并且埋入源/分级结的接合点降低带对带隧穿泄漏。

3. 发明授权

US07593268B2 Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage 有权
标题翻译：使用反向偏置电压擦除现场可编程门阵列的可编程互连单元的方法
公开(公告)号：US07593268B2
公开(公告)日：2009-09-22
申请号：US11567625
申请日：2006-12-06
申请人： Volker Hecht , John McCollum , Robert M. Salter, III
发明人： Volker Hecht , John McCollum , Robert M. Salter, III
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , H03K19/17748 , H03K19/1776
摘要： A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.
摘要翻译：一种用于擦除FPGA中的非易失性存储单元互连开关的方法，包括提供具有包含多个非易失性存储单元互连开关的核的FPGA，每个开关形成在开关阱区中并耦合到源/ 形成在与开关阱区域分离的接地阱区域中的n沟道晶体管的漏极。选择非易失性存储单元互连开关进行擦除。开关井区域与地面断开。将VCC电位施加到开关阱区域和与其耦合的n沟道晶体管的漏极，并且将擦除电位施加到所选择的非易失性存储器单元互连开关的栅极。

4. 发明授权

US08244791B1 Fast carry lookahead circuits 有权
标题翻译：快速携带查找电路
公开(公告)号：US08244791B1
公开(公告)日：2012-08-14
申请号：US12022721
申请日：2008-01-30
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

5. 发明授权

US07919977B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07919977B2
公开(公告)日：2011-04-05
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

6. 发明申请

US20060244485A1 THREE INPUT FIELD PROGRAMMABLE GATE ARRAY LOGIC CIRCUIT CONFIGURABLE AS A THREE INPUT LOOK UP TABLE, A D-LATCH OR A D FLIP-FLOP 失效
标题翻译：三个输入现场可编程门阵列逻辑电路可配置为三个输入查看表，D-LATCH或A D FLIP FLOP
公开(公告)号：US20060244485A1
公开(公告)日：2006-11-02
申请号：US11426158
申请日：2006-06-23
申请人： Alan Reynolds , Andrew Reynolds , Volker Hecht
发明人： Alan Reynolds , Andrew Reynolds , Volker Hecht
IPC分类号： H03K19/177
CPC分类号： H03K19/1733 , H03K19/17728
摘要： A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.
摘要翻译：现场可编程门阵列逻辑单元包括具有三个输入的逻辑电路和至少一个具有输入和输出的输出和多个复用器。逻辑电路还包括耦合在三个输入之间的多个可编程元件和逻辑电路的至少一个输出以及多个多路复用器的输入和输出，使得可以通过编程实现多个顺序逻辑单元和组合单元可选择的可编程元件，顺序逻辑单元可以包括触发器。

7. 发明授权

US07106100B1 Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop 失效
公开(公告)号：US07106100B1
公开(公告)日：2006-09-12
申请号：US10877872
申请日：2004-06-24
申请人： Alan B. Reynolds , Andrew W. Reynolds , Volker Hecht
发明人： Alan B. Reynolds , Andrew W. Reynolds , Volker Hecht
IPC分类号： G06F7/38
CPC分类号： H03K19/1733 , H03K19/17728
摘要： A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

8. 发明授权

US07884640B2 PLD providing soft wakeup logic 有权
标题翻译： PLD提供软唤醒逻辑
公开(公告)号：US07884640B2
公开(公告)日：2011-02-08
申请号：US12340358
申请日：2008-12-19
申请人： Jonathan W Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
发明人： Jonathan W Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
IPC分类号： H03K19/173
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译：公开了具有多个可编程区域的可编程逻辑器件（PLD）。一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

9. 发明授权

US07804321B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07804321B2
公开(公告)日：2010-09-28
申请号：US12205656
申请日：2008-09-05
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

10. 发明申请

US20080218206A1 FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK 审中-公开
标题翻译：现场可编程门阵列长路径路由网络
公开(公告)号：US20080218206A1
公开(公告)日：2008-09-11
申请号：US12127516
申请日：2008-05-27
申请人： Volker Hecht
发明人： Volker Hecht
IPC分类号： H03K19/177 , H04B3/36
CPC分类号： H03K19/17736
摘要： A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing lines, and the input of each of the plurality of buffers is connected to one of a first set of programmable switches, one of a second set of programmable switches, one of a third set of programmable switches, and one of a fourth set of programmable switches, and each one of the first set of programmable switches is connected to a separate one of the second set of programmable switches and a separate one of the second set of programmable switches, none of which are connected to an input of a same one of the plurality of buffers. Each one of the first set of programmable switches is connected to a separate routing line for transmitting a signal in a separate direction of a second set of routing lines.
摘要翻译：多方向路由中继器具有多个缓冲器，多个缓冲器中的每一个具有输入和输出。多个缓冲器中的每一个的输出被连接到单独的路由线路，用于在第一组路由线路的单独方向上发送信号，并且多个缓冲器中的每一个的输入连接到第一组的可编程开关，第二组可编程开关之一，第三组可编程开关之一和第四组可编程开关之一，并且第一组可编程开关中的每一个连接到第二组可编程开关和第二组可编程开关中的单独一个，其中没有一个连接到多个缓冲器中的相同的一个缓冲器的输入端。第一组可编程开关中的每一个连接到用于在第二组路由线的单独方向上发送信号的分离的路线。

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