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1. 发明授权

US6137728A Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor 有权
标题翻译：非易失性可重新编程的互连单元，具有可编程的埋入式源/漏极，在感应晶体管中
公开(公告)号：US6137728A
公开(公告)日：2000-10-24
申请号：US205678
申请日：1998-12-04
申请人： Jack Zezhong Peng , Volker Hecht , Robert M. Salter, III , Kyung Joon Han , Robert U. Broze
发明人： Jack Zezhong Peng , Volker Hecht , Robert M. Salter, III , Kyung Joon Han , Robert U. Broze
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11803 , G11C16/0441 , H01L27/115
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.
摘要翻译：公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。通过对公共控制栅极线和感测晶体管的源极/漏极的电压偏置来实现单元的编程。感测场效应晶体管的源极/漏极由在形成多晶硅浮置栅极和控制栅极之前形成的掩埋掺杂层（例如P掺杂衬底中的N +）形成。掺杂剂从掩埋源/漏极到浮置栅极下方的沟道的横向扩散有助于在擦除和编程操作期间的电子隧穿，并且埋入源/分级结的接合点降低带对带隧穿泄漏。

2. 发明授权

US5894148A Floating gate FPGA cell with counter-doped select device 失效
标题翻译：具有反掺杂选择器件的浮栅FPGA单元
公开(公告)号：US5894148A
公开(公告)日：1999-04-13
申请号：US708074
申请日：1996-08-09
申请人： Jack Zezhong Peng , Robert U. Broze , Kyung Joon Han , Victor Levchenko
发明人： Jack Zezhong Peng , Robert U. Broze , Kyung Joon Han , Victor Levchenko
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/7885
摘要： The present invention provides for an improved EPROM transistor cell which forms the programming portion of the programmable interconnect interconnect of an FPGA integrated circuit, and a method of manufacturing the EPROM cell. The EPROM cell has a floating gate disposed over a P region of the substrate. Aligned with one edge of the floating gate and at the surface of the substrate is a lightly doped P- region; on the opposite edge of the floating gate is a heavily doped N+ region. A control gate lies over the P-, P substrate and over the N+ region. N+ regions are formed at the opposite edges of the control gate. One N+ region is contiguous to the P- region and forms the source of the EPROM cell and the other N+ region is connected to the N+ region under the control gate and forms the drain of the EPROM cell. This structure allows for easy process control of the V.sub.T of the access transistor formed by the control gate and the P- surface, and of the space charge region formed by the P substrate and the N+ drain of the EPROM cell.
摘要翻译：本发明提供了形成FPGA集成电路的可编程互连互连的编程部分的改进的EPROM晶体管单元以及制造EPROM单元的方法。 EPROM单元具有设置在基板的P区上方的浮置栅极。与浮动栅极的一个边缘并且在衬底的表面处对准的是轻掺杂的P-区域; 在浮置栅极的相对边缘上是重掺杂的N +区域。控制门位于P，P衬底和N +区上方。 N +区域形成在控制栅极的相对边缘处。一个N +区域与P-区域相邻并形成EPROM单元的源极，另一个N +区域连接到控制栅极下面的N +区域，并形成EPROM单元的漏极。这种结构允许由控制栅极和P-表面形成的存取晶体管的VT以及由P基板和EPROM单元的N +漏极形成的空间电荷区域的VT的容易的过程控制。

3. 发明授权

US6072720A Nonvolatile reprogrammable interconnect cell with programmable buried bitline 有权
标题翻译：具有可编程掩埋位线的非易失性可编程互连单元
公开(公告)号：US6072720A
公开(公告)日：2000-06-06
申请号：US205876
申请日：1998-12-04
申请人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
发明人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
IPC分类号： G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/11524
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.
摘要翻译：公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。单元的编程通过与开关晶体管和感测晶体管并置的埋入位线来实现，开关晶体管和浮动栅极和控制栅极在其上。感测晶体管可以与开关晶体管的制造同时制造，由此两个晶体管的掺杂剂浓度相同。

4. 发明授权

US5764096A General purpose, non-volatile reprogrammable switch 失效
标题翻译：通用，非易失性可编程开关
公开(公告)号：US5764096A
公开(公告)日：1998-06-09
申请号：US754116
申请日：1996-11-21
申请人： Robert J. Lipp , Richard D. Freeman , Robert U. Broze , John M. Caywood , Joseph G. Nolan, III
发明人： Robert J. Lipp , Richard D. Freeman , Robert U. Broze , John M. Caywood , Joseph G. Nolan, III
IPC分类号： G11C16/04 , H03K19/173 , G11C11/34
CPC分类号： H03K19/1736 , G11C16/0441
摘要： A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.
摘要翻译：一个可编程互连，将独立的开关晶体管与独立的NVM编程和擦除元件紧密集成。编程元件是EPROM晶体管，擦除元件是Fowler-Nordheim隧穿器件。一个单一的浮动栅极由开关晶体管和NVM编程和对浮动栅极充电和放电的元件共享。共享浮栅结构是集成可编程互连的存储器结构，并控制开关晶体管的阻抗。

5. 发明授权

US5633518A Nonvolatile reprogrammable interconnect cell with FN tunneling and programming method thereof 失效
标题翻译：具有FN隧道及其编程方法的非易失性可编程互连单元
公开(公告)号：US5633518A
公开(公告)日：1997-05-27
申请号：US508914
申请日：1995-07-28
申请人： Robert U. Broze
发明人： Robert U. Broze
IPC分类号： G11C16/04 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11517 , H01L27/115 , H01L29/7883
摘要： An array of programmable interconnect cells, each cell having a floating gate as the gate of an MOS switch transistor which programmably connect or disconnects nodes, is used in an FPGA. The floating gate of each cell, which is capacitively coupled to a control gate, is programmed by Fowler-Nordheim tunneling through an tunneling oxide above a programming/erase line in the integrated circuit substrate. Contiguous and parallel to the programming/erase line is at least one tunneling control line which forms a PN junction in close proximity to the programming/erase line region under the tunneling oxide. Under a reverse bias, a deep charge depletion region is formed in the programming/erase line region to block tunneling. In this manner, a selected cell can be programmed/erased, while the non-selected cells are not.
摘要翻译：在FPGA中使用可编程互连单元的阵列，每个单元具有浮动栅极作为可编程地连接或断开节点的MOS开关晶体管的栅极。电容耦合到控制栅极的每个电池的浮动栅极由Fowler-Nordheim通过穿过集成电路衬底中的编程/擦除线路上的隧道氧化物进行隧道编程。与编程/擦除线相连和并联的是至少一个隧道控制线，其在隧道氧化物下方的编程/擦除线区域附近形成PN结。在反向偏压下，在编程/擦除线区域中形成深电荷耗尽区，以阻止隧穿。以这种方式，可以对所选择的单元进行编程/擦除，而未选择的单元不被编程。

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