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    • 2. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20080042214A1
    • 2008-02-21
    • US11892053
    • 2007-08-20
    • Daisaku IkomaAtsuhiro KajiyaKatsuhiro OotaniKyoji Yamashita
    • Daisaku IkomaAtsuhiro KajiyaKatsuhiro OotaniKyoji Yamashita
    • H01L27/092H01L29/78
    • H01L21/76895H01L21/823475H01L27/0207
    • A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
    • 半导体器件包括半导体衬底; 扩散区,其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件,并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触,连接到栅极互连部分,并且具有大于栅极互连部分的栅极长度方向的尺寸。
    • 3. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07279727B2
    • 2007-10-09
    • US11148208
    • 2005-06-09
    • Daisaku IkomaAtsuhiro KajiyaKatsuhiro OotaniKyoji Yamashita
    • Daisaku IkomaAtsuhiro KajiyaKatsuhiro OotaniKyoji Yamashita
    • H01L27/10
    • H01L21/76895H01L21/823475H01L27/0207
    • A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
    • 半导体器件包括半导体衬底; 扩散区,其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件,并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触,连接到栅极互连部分,并且具有大于栅极互连部分的栅极长度方向的尺寸。
    • 4. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20060017070A1
    • 2006-01-26
    • US11148208
    • 2005-06-09
    • Daisaku IkomaAtsuhiro KajiyaKatsuhiro OotaniKyoji Yamashita
    • Daisaku IkomaAtsuhiro KajiyaKatsuhiro OotaniKyoji Yamashita
    • H01L29/76
    • H01L21/76895H01L21/823475H01L27/0207
    • A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
    • 半导体器件包括半导体衬底; 扩散区,其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件,并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触,连接到栅极互连部分,并且具有大于栅极互连部分的栅极长度方向的尺寸。
    • 5. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07709900B2
    • 2010-05-04
    • US11892053
    • 2007-08-20
    • Daisaku IkomaAtsuhiro KajiyaKatsuhiro OotaniKyoji Yamashita
    • Daisaku IkomaAtsuhiro KajiyaKatsuhiro OotaniKyoji Yamashita
    • H01L23/62
    • H01L21/76895H01L21/823475H01L27/0207
    • A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
    • 半导体器件包括半导体衬底; 扩散区,其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件,并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触,连接到栅极互连部分,并且具有大于栅极互连部分的栅极长度方向的尺寸。
    • 9. 发明授权
    • Semiconductor device and manufacturing method thereof
    • 半导体装置及其制造方法
    • US5396096A
    • 1995-03-07
    • US132323
    • 1993-10-06
    • Susumu AkamatsuAtsuhiro Kajiya
    • Susumu AkamatsuAtsuhiro Kajiya
    • H01L21/762H01L21/8238H01L27/092H01L29/78H01L21/265
    • H01L21/823807H01L21/76218H01L27/0928
    • In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.
    • 在半导体装置中,在半导体基板上设置FET和隔离,在隔离下设置沟道停止区域。 至少一个施加FET的源极区域和漏极区域的高电压的区域与沟道停止区域分离,并且在其间提供掺杂有用于调节阈值电平的杂质的第一缓冲区域。 在栅电极下方并且与隔离相邻的区域用作掺杂用于调整阈值电平的杂质的第二缓冲区域。 利用第一缓冲区域,确保漏极区域和沟道停止区域的边界处的耗尽区域,从而获得对源极/漏极区域的高电压的优异的耐久性。 利用第二缓冲区域,防止源极区域和漏极区域之间的漏电流。