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1. 发明授权

US07554163B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07554163B2
公开(公告)日：2009-06-30
申请号：US11481909
申请日：2006-07-07
申请人： Takayuki Yamada , Atsuhiro Kajiya , Satoshi Ishikura
发明人： Takayuki Yamada , Atsuhiro Kajiya , Satoshi Ishikura
IPC分类号： H01L29/76
CPC分类号： H01L27/11 , H01L27/0203 , Y10S257/903
摘要： A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.
摘要翻译：第一半导体区域沿着栅极长度方向的宽度比第二半导体区域小。在这种情况下，第一半导体区域沿栅极宽度方向的宽度比第二半导体区域宽。

2. 发明申请

US20070007603A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070007603A1
公开(公告)日：2007-01-11
申请号：US11481909
申请日：2006-07-07
申请人： Takayuki Yamada , Atsuhiro Kajiya , Satoshi Ishikura
发明人： Takayuki Yamada , Atsuhiro Kajiya , Satoshi Ishikura
IPC分类号： H01L29/76
CPC分类号： H01L27/11 , H01L27/0203 , Y10S257/903
摘要： A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.
摘要翻译：第一半导体区域沿栅极长度方向具有比第二半导体区域更小的宽度。在这种情况下，第一半导体区域沿栅极宽度方向的宽度比第二半导体区域宽。

3. 发明授权

US07859058B2 Semiconductor device having a SRAM with a substrate contact and method for fabricating the same 有权
标题翻译：具有具有基板接触的SRAM的半导体器件及其制造方法
公开(公告)号：US07859058B2
公开(公告)日：2010-12-28
申请号：US11480909
申请日：2006-07-06
申请人： Masayuki Nakamura , Satoshi Ishikura , Takayuki Yamada
发明人： Masayuki Nakamura , Satoshi Ishikura , Takayuki Yamada
IPC分类号： H01L27/088
CPC分类号： H01L27/11
摘要： An isolation insulating film is formed so that an active region of a first access transistor and a substrate contact region can be integrated with each other in a plan view. A dummy gate electrode is formed on the semiconductor substrate between the active region of the first access transistor and the substrate contact region. The dummy gate electrode is electrically connected to a P-type impurity region of the substrate contact region.
摘要翻译：形成隔离绝缘膜，使得第一存取晶体管和基板接触区域的有源区域可以在平面图中彼此一体化。在第一存取晶体管的有源区和衬底接触区之间的半导体衬底上形成伪栅电极。虚拟栅电极与衬底接触区域的P型杂质区电连接。

4. 发明申请

US20070007617A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070007617A1
公开(公告)日：2007-01-11
申请号：US11480909
申请日：2006-07-06
申请人： Masayuki Nakamura , Satoshi Ishikura , Takayuki Yamada
发明人： Masayuki Nakamura , Satoshi Ishikura , Takayuki Yamada
IPC分类号： H01L29/00 , G11C11/00
CPC分类号： H01L27/11
摘要： An isolation insulating film is formed so that an active region of a first access transistor and a substrate contact region can be integrated with each other in a plan view. A dummy gate electrode is formed on the semiconductor substrate between the active region of the first access transistor and the substrate contact region. The dummy gate electrode is electrically connected to a P-type impurity region of the substrate contact region.
摘要翻译：形成隔离绝缘膜，使得第一存取晶体管和基板接触区域的有源区域可以在平面图中彼此一体化。在第一存取晶体管的有源区和衬底接触区之间的半导体衬底上形成伪栅电极。虚拟栅电极与衬底接触区域的P型杂质区电连接。

5. 发明授权

US08077530B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08077530B2
公开(公告)日：2011-12-13
申请号：US13084026
申请日：2011-04-11
申请人： Satoshi Ishikura , Marefusa Kurumada , Hiroaki Okuyama , Yoshinobu Yamagami , Toshio Terano
发明人： Satoshi Ishikura , Marefusa Kurumada , Hiroaki Okuyama , Yoshinobu Yamagami , Toshio Terano
IPC分类号： G11C5/02 , G11C5/06 , G11C7/22 , G11C7/10
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。

6. 发明授权

US07692955B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07692955B2
公开(公告)日：2010-04-06
申请号：US12039585
申请日：2008-02-28
申请人： Yutaka Terada , Satoshi Ishikura , Yoshinobu Yamagami , Toshio Terano
发明人： Yutaka Terada , Satoshi Ishikura , Yoshinobu Yamagami , Toshio Terano
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/41
摘要： A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.
摘要翻译：半导体集成电路包括：包括多个SRAM存储单元的存储单元阵列; 包括并联连接的多个晶体管电路的特性测量电路; 和第一个终端。多个晶体管电路各自包括以与包括在SRAM存储单元之一中的晶体管中的一个相同的方式配置的第一晶体管。第一晶体管被连接以便根据提供给第一晶体管的栅极的电压来控制第一端子和参考电位的节点之间的电流。

7. 发明申请

US20080037337A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20080037337A1
公开(公告)日：2008-02-14
申请号：US11889140
申请日：2007-08-09
申请人： Toshikazu Suzuki , Satoshi Ishikura
发明人： Toshikazu Suzuki , Satoshi Ishikura
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A semiconductor memory includes a plurality of memory cells, each of which includes a first inverter connected to one of high-data retaining supply lines which constitute one of high-data retaining supply line pairs corresponding to the memory cell and a second inverter connected to the other one of the high-data retaining supply lines which constitute the corresponding high-data retaining supply line pair, an input and output of the second inverter being connected to an output and input of the first inverter, respectively. A selected high-data retaining supply circuit receives a signal determined according to an input data signal and address signal without the intervention of any of the bit lines which constitute the bit line pairs to drive the connected high-data retaining supply lines such that it has a potential corresponding to the received signal.
摘要翻译：半导体存储器包括多个存储单元，每个存储单元包括连接到构成与存储单元对应的高数据保持供电线对之一的高数据保持电源线之一的第一反相器和连接到存储单元的第二反相器构成相应的高数据保持电源线对的高数据保持电源线中的另一个，第二反相器的输入和输出分别连接到第一反相器的输出和输入。选择的高数据保持电源电路接收根据输入数据信号和地址信号确定的信号，而不需要介入构成位线对的任何位线来驱动连接的高数据保持电源线，使得其具有对应于接收信号的电位。

8. 发明授权

US5849169A Method for electrically coloring aluminum material and gray-colored aluminum material obtained thereby 失效
标题翻译：由此获得的铝材料和灰色铝材料的电解着色方法
公开(公告)号：US5849169A
公开(公告)日：1998-12-15
申请号：US972506
申请日：1997-11-18
申请人： Kazuo Aikawa , Satoshi Ishikura , Makoto Kato
发明人： Kazuo Aikawa , Satoshi Ishikura , Makoto Kato
IPC分类号： C25D11/22
CPC分类号： C25D11/22
摘要： Disclosed are a method for electrolytically coloring an aluminum material which is capable of coloring an anodic oxide film in a gray color and a gray-colored aluminum material obtained thereby. In a method for electrolytically coloring an aluminum material having the anodic oxide film formed on the surface thereof in an electrolytic coloring solution containing an inorganic metal salt, a strongly acidic electrolytic coloring solution containing sulfuric acid, stannous sulfate, nickel sulfate, and ammonium sulfate and having a pH of not more than 2.5 is used as the electrolytic coloring solution. Preferably the electrolytic coloring solution contains sulfuric acid at a concentration in the range of 3 to 30 g/liter, stannous sulfate at a concentration in the range of 0.1 to 3.0 g/liter, nickel sulfate at a concentration in the range of 10 to 100 g/liter, and ammonium sulfate at a concentration in the range of 20 to 100 g/liter. By this method, a gray-colored aluminum material possessed of an anodic oxide film colored in an achromatic or substantially achromatic gray color is obtained.
摘要翻译：公开了一种能够使由灰色产生的阳极氧化膜着色的铝材料电解着色的方法和由此获得的灰色铝材料。在含有无机金属盐的电解着色溶液表面上形成有阳极氧化膜的铝材的电解着色方法中，含有硫酸，硫酸亚锡，硫酸镍，硫酸铵的强酸性电解着色溶液，以及使用pH不大于2.5的电解着色溶液。电解着色溶液优选含有浓度范围为3〜30g / l的硫酸，浓度为0.1〜3.0g / l的硫酸亚锡，浓度为10〜100的硫酸镍 g /升，浓度为20〜100g / L的硫酸铵。通过该方法，获得具有以消色差或基本上无色的灰色着色的阳极氧化膜的灰色铝材料。

9. 发明授权

US08014191B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US08014191B2
公开(公告)日：2011-09-06
申请号：US12352838
申请日：2009-01-13
申请人： Toshikazu Suzuki , Yoshinobu Yamagami , Satoshi Ishikura
发明人： Toshikazu Suzuki , Yoshinobu Yamagami , Satoshi Ishikura
IPC分类号： G11C11/00
CPC分类号： G11C5/14 , G11C11/412
摘要： In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.
摘要翻译：在包括排列成矩阵的字线和位线的半导体存储器以及设置在字线和位线的交叉处的多个存储单元的情况下，提供位线预充电电路，用于控制低数据保持电力的电位电源耦合到提供在对应的一个位线上的存储器单元。在写入操作中，位线预充电电路控制与所选位线对应的存储单元的低数据保持电源的电位高于对应于存储单元的低数据保持电源的电位到未选择的位线。

10. 发明授权

US07872893B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07872893B2
公开(公告)日：2011-01-18
申请号：US11961166
申请日：2007-12-20
申请人： Marefusa Kurumada , Satoshi Ishikura , Toshio Terano
发明人： Marefusa Kurumada , Satoshi Ishikura , Toshio Terano
IPC分类号： G11C5/06
CPC分类号： G11C11/413
摘要： A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.
摘要翻译：具有分层位线结构的半导体存储器件包括存储单元和用于经由位线放大从一个存储单元读取的信号的放大电路。连续地形成其中形成有存储单元的P沟道晶体管的单元N阱区域和形成放大电路的P沟道晶体管的放大电路N阱区域。

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