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1. 发明授权

US07546491B2 Semiconductor memory device with standby current failure judging function and method for judging standby current failure 有权
标题翻译：具有待机电流故障判断功能的半导体存储器件和用于判断待机电流故障的方法
公开(公告)号：US07546491B2
公开(公告)日：2009-06-09
申请号：US10802210
申请日：2004-03-17
申请人： Young-Ho Suh , Kyo-Min Sohn
发明人： Young-Ho Suh , Kyo-Min Sohn
IPC分类号： G06F11/00
CPC分类号： G11C29/83 , G11C29/02 , G11C29/025 , G11C29/832 , G11C2029/5006
摘要： A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a repair unit. A selection circuit outputs selection signals for selecting the memory cells of the array in the repair unit in response to a row address in a test operation mode. A power switch circuit operates in response to the selection signals, and connects the second power line connected to the selected memory cells with the first power line in the test operation mode. The power switch circuit disconnects the remaining second power lines from the first power line.
摘要翻译：一种用于接收电源电压的焊盘，连接到焊盘的第一电力线和分别连接到修复单元的存储单元的多个第二电力线的半导体存储器件。选择电路响应于测试操作模式中的行地址输出用于在修复单元中选择阵列的存储单元的选择信号。电源开关电路响应于选择信号而工作，并且在测试操作模式下将连接到所选择的存储单元的第二电力线与第一电力线连接。电源开关电路将剩余的第二电源线与第一电源线断开。

2. 发明授权

US06826088B2 Method and integrated circuit capable of reading and writing data simultaneously 有权
标题翻译：能够同时读写数据的方法和集成电路
公开(公告)号：US06826088B2
公开(公告)日：2004-11-30
申请号：US10692997
申请日：2003-10-24
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G11C700
CPC分类号： G11C11/4076 , G06F12/0893 , G06F2212/3042 , G11C7/22 , G11C2207/2245 , G11C2207/2281 , G11C2207/229
摘要： An integrated circuit and a method of reading and writing data at the same time are provided. The integrated circuit has separate input and output ports and a write address and a read address are input during a period of a clock signal. The circuit includes memory blocks that respectively include a plurality of sub memory blocks, cache memory blocks that respectively correspond to the memory blocks, and a tag memory control unit. The tag memory control unit controls reading data from and writing data to the memory blocks and the cache memory blocks in response to the write address or the read address. In particular, reads of the data from or writes of the data to the memory block and the cache memory block at the same time are performed if an upper address of the read address and an upper address of the write address are identical to each other. Since data can be separately read from and written to a memory block or a cache memory block at the same time during a period of a clock signal, an operational frequency of the clock signal can be increased.
摘要翻译：提供了同时读取和写入数据的集成电路和方法。集成电路具有单独的输入和输出端口，并且在时钟信号的周期期间输入写入地址和读取地址。电路包括分别包括多个子存储器块，分别对应于存储器块的高速缓存存储器块和标签存储器控制单元的存储器块。标签存储器控制单元响应于写入地址或读取地址控制从存储器块和高速缓冲存储器块读取数据并将数据写入高速缓存存储器块。特别地，如果读地址的高地址和写地址的高地址彼此相同，则执行数据从同时读取到数据到存储器块和高速缓冲存储块的数据。由于可以在时钟信号的周期期间同时分别读取和写入存储器块或高速缓存存储器块，所以可以增加时钟信号的工作频率。

3. 发明授权

US06618299B2 Semiconductor memory device with redundancy 有权
标题翻译：具有冗余的半导体存储器件
公开(公告)号：US06618299B2
公开(公告)日：2003-09-09
申请号：US09946744
申请日：2001-09-05
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/846
摘要： A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.
摘要翻译：具有不具有性能损失的冗余的半导体存储器件。具有冗余的半导体存储器件包括默认阵列; 一行冗余阵列块与默认阵列分离，并提供行冗余阵列，用于弥补行方向的不足; 一列与冗余阵列块相隔离的缺省阵列，并提供列冗余阵列，弥补列中的不足; 控制块向默认阵列，行冗余阵列和列冗余阵列共同提供控制信号; 以及用于接收地址和控制信号以产生冗余阵列所需的控制信号并确定是否访问冗余阵列的冗余计算块，并且在冗余阵列访问期间产生禁用默认阵列的读出放大器的信号。

4. 发明授权

US06150873A Internal voltage converter for low operating voltage semiconductor memory 有权
标题翻译：用于低工作电压半导体存储器的内部电压转换器
公开(公告)号：US06150873A
公开(公告)日：2000-11-21
申请号：US288771
申请日：1999-04-08
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G11C11/413 , G05F1/46 , G05F1/56 , G11C11/407 , H01L27/07 , G05F3/02
CPC分类号： G05F1/465
摘要： The present invention provides an internal voltage converter that comprises a voltage down converter which receives an external voltage and provides an intermediate voltage that is stable and lower than the external voltage. The intermediate voltage is used to operate a clock signal generator and a timing controller that produces a timing signal. The regulator also includes a booster that receives the timing signal and the external voltage, and outputs a boosted voltage that is of a lower level than in the prior art. The regulator also includes a voltage source that receives the boosted voltage and the external voltage, and outputs the device's internal operating voltage for operating it.
摘要翻译：本发明提供一种内部电压转换器，其包括接收外部电压并提供稳定且低于外部电压的中间电压的降压转换器。中间电压用于操作产生定时信号的时钟信号发生器和定时控制器。调节器还包括接收定时信号和外部电压的升压器，并输出比现有技术低的升压电压。调节器还包括一个接收升压电压和外部电压的电压源，并输出器件的内部工作电压进行操作。

5. 发明授权

US07415590B2 Integrated circuit having a memory cell array capable of simultaneously performing a data read operation and a data write operation 有权
标题翻译：具有能够同时执行数据读取操作和数据写入操作的存储单元阵列的集成电路
公开(公告)号：US07415590B2
公开(公告)日：2008-08-19
申请号：US10814968
申请日：2004-03-31
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C7/1075 , G11C8/16
摘要： An integrated circuit comprising a memory cell array capable of simultaneously performing data read and write operations is provided. The integrated circuit to which inputs and outputs (IOs) are separately provided and to which a write address and a read address are simultaneously input during one period of a clock signal comprises a plurality of memory blocks, the memory blocks comprising a plurality of sub-memory blocks, a plurality of data memory blocks corresponding to the memory blocks, and a tag memory controlling unit, which writes data to the memory blocks or reads data from the memory blocks in response to the write address or the read address, wherein access to the same sub-memory block is not simultaneously performed when the write address and the read address are the same.
摘要翻译：提供一种包括能够同时执行数据读写操作的存储单元阵列的集成电路。分别提供输入和输出（IO）的集成电路并且在时钟信号的一个周期期间同时输入写地址和读地址的集成电路包括多个存储块，所述存储块包括多个子区，存储器块，对应于存储块的多个数据存储块，以及标签存储器控制单元，其响应于写入地址或读取地址将数据写入存储器块或从存储器块读取数据，其中访问当写入地址和读取地址相同时，不会同时执行相同的子存储器块。

6. 发明授权

US07193903B2 Method of controlling an integrated circuit capable of simultaneously performing a data read operation and a data write operation 有权
标题翻译：控制能够同时执行数据读取操作和数据写入操作的集成电路的方法
公开(公告)号：US07193903B2
公开(公告)日：2007-03-20
申请号：US10811613
申请日：2004-03-29
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G11C7/10
CPC分类号： G11C8/16 , G11C7/22
摘要： A method of controlling an integrated circuit (IC) capable of simultaneously performing a data read operation and a data write operation is provided. The method comprises (a) receiving a write address, a read address, and write data, (b) determining, a memory block and a data memory block in which a data read operation and a data write operation are to be performed in response to the write address and the read address, (c) performing the data read operation or the data write operation in the data memory block according to the determination of step (b), and (d) performing the data read operation or the data write operation in the memory block according to the determination of step (b).
摘要翻译：提供一种控制能够同时执行数据读取操作和数据写入操作的集成电路（IC）的方法。该方法包括：（a）接收写入地址，读取地址和写入数据，（b）确定存储器块和数据存储器块，其中将响应于数据读取操作和数据写入操作执行数据读取操作和数据写入操作写入地址和读取地址，（c）根据步骤（b）的确定执行数据存储块中的数据读取操作或数据写入操作，以及（d）执行数据读取操作或数据写入操作根据步骤（b）的确定在存储器块中。

7. 发明授权

US06271718B1 Internal voltage converter for low operating voltage semiconductor memory 有权
标题翻译：用于低工作电压半导体存储器的内部电压转换器
公开(公告)号：US06271718B1
公开(公告)日：2001-08-07
申请号：US09675125
申请日：2000-09-28
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G05F302
CPC分类号： G05F1/465
摘要： The present invention provides an internal voltage converter that comprises a voltage down converter which receives an external voltage and provides an intermediate voltage that is stable and lower than the external voltage. The intermediate voltage is used to operate a clock signal generator and a timing controller that produces a timing signal. The regulator also includes a booster that receives the timing signal and the external voltage, and outputs a boosted voltage that is of a lower level than in the prior art. The regulator also includes a voltage source that receives the boosted voltage and the external voltage, and outputs the device's internal operating voltage for operating it.
摘要翻译：本发明提供一种内部电压转换器，其包括接收外部电压并提供稳定且低于外部电压的中间电压的降压转换器。中间电压用于操作产生定时信号的时钟信号发生器和定时控制器。调节器还包括接收定时信号和外部电压的升压器，并输出比现有技术低的升压电压。调节器还包括一个接收升压电压和外部电压的电压源，并输出器件的内部工作电压进行操作。

8. 发明申请

US20090018698A1 ROBOT SYSTEM BASED ON NETWORK AND EXECUTION METHOD OF THAT SYSTEM 审中-公开
标题翻译：基于网络的机器人系统及其系统的执行方法
公开(公告)号：US20090018698A1
公开(公告)日：2009-01-15
申请号：US11720397
申请日：2005-04-27
申请人： Hyun Kim , Kang-Woo Lee , Joo-Haeng Lee , Tae-Gun Kang , Ae-Kyeung Moon , Young-Ho Suh , Joon-Myun Cho , Young-Jo Cho
发明人： Hyun Kim , Kang-Woo Lee , Joo-Haeng Lee , Tae-Gun Kang , Ae-Kyeung Moon , Young-Ho Suh , Joon-Myun Cho , Young-Jo Cho
IPC分类号： G06F19/00
CPC分类号： G05D1/0011
摘要： The present invention relates to a network-based robot system and an executing method thereof. According to an exemplary embodiment of the present invention, predefine environment information is expressed in a universal data model (UDM) described by a linkage that shows a relationship among nodes, each node being an object of a virtual space abstracted by a real physical space. The universal data model is updated based on the context information, event occurrence information is transmitted to a task engine when the context information data value is changed, and the task engine executes a corresponding task through reasoning and invokes an external service. The robot can better recognize the context information by utilizing the external sensing function and external processing function. In addition, the robot system can provide an active service by reasoning the recognized context information and obtaining high-level information.
摘要翻译：本发明涉及基于网络的机器人系统及其执行方法。根据本发明的示例性实施例，预定义环境信息在由链接描述的通用数据模型（UDM）中表示，所述链接显示节点之间的关系，每个节点是由真实物理空间抽象的虚拟空间的对象。基于上下文信息来更新通用数据模型，当上下文信息数据值改变时事件发生信息被发送到任务引擎，并且任务引擎通过推理执行对应的任务并调用外部服务。机器人可以通过利用外部感应功能和外部处理功能，更好地识别上下文信息。此外，机器人系统可以通过推断识别的上下文信息并获得高级信息来提供主动服务。

9. 发明授权

US07304908B2 SRAM device capable of performing burst operation 有权
标题翻译：能够执行突发操作的SRAM器件
公开(公告)号：US07304908B2
公开(公告)日：2007-12-04
申请号：US11333650
申请日：2006-01-17
申请人： Young-Ho Suh
发明人： Young-Ho Suh
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/1018 , G11C7/1051 , G11C7/1063 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C2207/2245
摘要： Memory devices are provided which are capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single wordline, and which are capable of controlling data input/output for interruption of burst operation interruptions without having to employ complex control circuitry.
摘要翻译：提供存储器件，其能够响应于单个字线的选择而同时向存储器写入/读取多个数据位，并且能够控制数据输入/输出用于中断突发操作，从而执行突发操作中断而不必使用复杂的控制电路。

10. 发明授权

US07263023B2 Semiconductor memory device having memory architecture supporting hyper-threading operation in host system 有权
标题翻译：具有支持主机系统中的超线程操作的存储器架构的半导体存储器件
公开(公告)号：US07263023B2
公开(公告)日：2007-08-28
申请号：US11119687
申请日：2005-05-03
申请人： Young-Ho Suh
发明人： Young-Ho Suh
IPC分类号： G11C8/00
CPC分类号： G11C7/1042 , G11C7/22 , G11C8/12 , G11C8/16
摘要： A semiconductor memory device and a method of operating the semiconductor memory device are disclosed. The semiconductor memory device comprises a memory cell array having a plurality of cell array blocks. The cell array blocks are operationally divided into a plurality of memory planes using a memory determining unit. Each of the memory planes comprises at least one cell array block and is capable of executing independent data access operations using an independent operating mode.
摘要翻译：公开了一种半导体存储器件和操作半导体存储器件的方法。半导体存储器件包括具有多个单元阵列块的存储单元阵列。使用存储器确定单元将单元阵列块可操作地划分为多个存储器平面。每个存储器平面包括至少一个单元阵列块，并且能够使用独立的操作模式来执行独立的数据访问操作。

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