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1. 发明申请

US20150243374A1 DEVICE AND METHOD FOR REPAIRING MEMORY CELL AND MEMORY SYSTEM INCLUDING THE DEVICE 有权
标题翻译：用于修复包含设备的存储器单元和存储器系统的装置和方法
公开(公告)号：US20150243374A1
公开(公告)日：2015-08-27
申请号：US14698219
申请日：2015-04-28
申请人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
发明人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
IPC分类号： G11C29/00 , G11C8/10 , G11C8/06 , G11C17/16 , G11C17/18
CPC分类号： G11C29/4401 , G01R31/3187 , G06F11/2053 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C8/06 , G11C8/10 , G11C11/40 , G11C11/4078 , G11C11/4094 , G11C11/4096 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/36 , G11C29/42 , G11C29/44 , G11C29/56 , G11C29/56008 , G11C29/78 , G11C29/785 , G11C2029/4402 , G11C2029/5606
摘要： Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
摘要翻译：提供了一种用于修复存储器测试系统中的存储单元的方法和装置。测试设备通过根据测试命令测试存储设备来检测故障地址，并将故障地址临时存储在故障地址存储器（FAM）中。故障地址根据故障地址传输模式发送到存储设备，被临时存储在存储器件的暂时失效地址存储器中，然后存储在作为非易失性存储设备的反熔丝阵列。为了确保数据的可靠性，可以读取存储的数据以验证数据，并且验证结果可以与测试设备串联或并行传输。

2. 发明申请

US20150221361A1 Semiconductor Memory Devices Including Redundancy Memory Cells 有权
标题翻译：包括冗余存储器单元的半导体存储器件
公开(公告)号：US20150221361A1
公开(公告)日：2015-08-06
申请号：US14503691
申请日：2014-10-01
申请人： Yun-Young Lee , Kyo-Min Sohn , Sang-Joon Hwang , Sung-Min Seo , Sang-Bo Lee , Nak-Won Heo
发明人： Yun-Young Lee , Kyo-Min Sohn , Sang-Joon Hwang , Sung-Min Seo , Sang-Bo Lee , Nak-Won Heo
IPC分类号： G11C11/406 , G11C11/408 , G11C17/16
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C17/16 , G11C29/44 , G11C29/783 , G11C29/785 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
摘要翻译：半导体存储器件包括存储单元阵列，修复控制电路和刷新控制电路。存储单元阵列包括多个存储单元和多个冗余存储单元。修复控制电路在修复模式期间接收修复命令并对多个存储单元中的第一有缺陷存储单元执行修复操作。半导体存储器件可以响应于修复命令在修复模式下操作。刷新控制电路在修复模式期间对多个存储单元中的无缺陷存储单元执行刷新操作。

3. 发明申请

US20130227344A1 DEVICE AND METHOD FOR REPAIRING MEMORY CELL AND MEMORY SYSTEM INCLUDING THE DEVICE 有权
公开(公告)号：US20130227344A1
公开(公告)日：2013-08-29
申请号：US13753165
申请日：2013-01-29
申请人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
发明人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
IPC分类号： G06F11/27 , G06F11/20
CPC分类号： G11C29/4401 , G01R31/3187 , G06F11/2053 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C8/06 , G11C8/10 , G11C11/40 , G11C11/4078 , G11C11/4094 , G11C11/4096 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/36 , G11C29/42 , G11C29/44 , G11C29/56 , G11C29/56008 , G11C29/78 , G11C29/785 , G11C2029/4402 , G11C2029/5606
摘要： Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

4. 发明申请

US20130061102A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130061102A1
公开(公告)日：2013-03-07
申请号：US13602906
申请日：2012-09-04
申请人： Kyo-min SOHN , Byung-sik MOON
发明人： Kyo-min SOHN , Byung-sik MOON
IPC分类号： G11C29/00
CPC分类号： G11C7/1063 , G11C7/1006
摘要： A semiconductor memory device including a data bus inversion (DBI) determination unit, a first inverter, a cyclic redundancy check (CRC) calculation unit, a second inverter, and a DQ pin. The DBI determination unit is configured to determine whether to perform DBI based on first data on a main data line and configured to generate DBI data. The first inverter is configured to invert or non-invert the first data according to the DBI data to generate second data. The CRC calculation unit is configured to generate CRC data based on the second data and the DBI data. The second inverter is configured to invert or non-invert the first data according to the DBI data to generate third data. The DQ pin is configured to output the third data externally.
摘要翻译：一种包括数据总线反相（DBI）确定单元，第一反相器，循环冗余校验（CRC）计算单元，第二反相器和DQ引脚的半导体存储器件。 DBI确定单元被配置为基于主数据线上的第一数据来确定是否执行DBI，并且被配置为生成DBI数据。第一反相器被配置为根据DBI数据反转或不反转第一数据以产生第二数据。 CRC计算单元被配置为基于第二数据和DBI数据生成CRC数据。第二反相器被配置为根据DBI数据反转或不反转第一数据以产生第三数据。 DQ引脚配置为从外部输出第三个数据。

5. 发明授权

US07546491B2 Semiconductor memory device with standby current failure judging function and method for judging standby current failure 有权
标题翻译：具有待机电流故障判断功能的半导体存储器件和用于判断待机电流故障的方法
公开(公告)号：US07546491B2
公开(公告)日：2009-06-09
申请号：US10802210
申请日：2004-03-17
申请人： Young-Ho Suh , Kyo-Min Sohn
发明人： Young-Ho Suh , Kyo-Min Sohn
IPC分类号： G06F11/00
CPC分类号： G11C29/83 , G11C29/02 , G11C29/025 , G11C29/832 , G11C2029/5006
摘要： A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a repair unit. A selection circuit outputs selection signals for selecting the memory cells of the array in the repair unit in response to a row address in a test operation mode. A power switch circuit operates in response to the selection signals, and connects the second power line connected to the selected memory cells with the first power line in the test operation mode. The power switch circuit disconnects the remaining second power lines from the first power line.
摘要翻译：一种用于接收电源电压的焊盘，连接到焊盘的第一电力线和分别连接到修复单元的存储单元的多个第二电力线的半导体存储器件。选择电路响应于测试操作模式中的行地址输出用于在修复单元中选择阵列的存储单元的选择信号。电源开关电路响应于选择信号而工作，并且在测试操作模式下将连接到所选择的存储单元的第二电力线与第一电力线连接。电源开关电路将剩余的第二电源线与第一电源线断开。

6. 发明授权

US06826088B2 Method and integrated circuit capable of reading and writing data simultaneously 有权
标题翻译：能够同时读写数据的方法和集成电路
公开(公告)号：US06826088B2
公开(公告)日：2004-11-30
申请号：US10692997
申请日：2003-10-24
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G11C700
CPC分类号： G11C11/4076 , G06F12/0893 , G06F2212/3042 , G11C7/22 , G11C2207/2245 , G11C2207/2281 , G11C2207/229
摘要： An integrated circuit and a method of reading and writing data at the same time are provided. The integrated circuit has separate input and output ports and a write address and a read address are input during a period of a clock signal. The circuit includes memory blocks that respectively include a plurality of sub memory blocks, cache memory blocks that respectively correspond to the memory blocks, and a tag memory control unit. The tag memory control unit controls reading data from and writing data to the memory blocks and the cache memory blocks in response to the write address or the read address. In particular, reads of the data from or writes of the data to the memory block and the cache memory block at the same time are performed if an upper address of the read address and an upper address of the write address are identical to each other. Since data can be separately read from and written to a memory block or a cache memory block at the same time during a period of a clock signal, an operational frequency of the clock signal can be increased.
摘要翻译：提供了同时读取和写入数据的集成电路和方法。集成电路具有单独的输入和输出端口，并且在时钟信号的周期期间输入写入地址和读取地址。电路包括分别包括多个子存储器块，分别对应于存储器块的高速缓存存储器块和标签存储器控制单元的存储器块。标签存储器控制单元响应于写入地址或读取地址控制从存储器块和高速缓冲存储器块读取数据并将数据写入高速缓存存储器块。特别地，如果读地址的高地址和写地址的高地址彼此相同，则执行数据从同时读取到数据到存储器块和高速缓冲存储块的数据。由于可以在时钟信号的周期期间同时分别读取和写入存储器块或高速缓存存储器块，所以可以增加时钟信号的工作频率。

7. 发明授权

US06618299B2 Semiconductor memory device with redundancy 有权
标题翻译：具有冗余的半导体存储器件
公开(公告)号：US06618299B2
公开(公告)日：2003-09-09
申请号：US09946744
申请日：2001-09-05
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/846
摘要： A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.
摘要翻译：具有不具有性能损失的冗余的半导体存储器件。具有冗余的半导体存储器件包括默认阵列; 一行冗余阵列块与默认阵列分离，并提供行冗余阵列，用于弥补行方向的不足; 一列与冗余阵列块相隔离的缺省阵列，并提供列冗余阵列，弥补列中的不足; 控制块向默认阵列，行冗余阵列和列冗余阵列共同提供控制信号; 以及用于接收地址和控制信号以产生冗余阵列所需的控制信号并确定是否访问冗余阵列的冗余计算块，并且在冗余阵列访问期间产生禁用默认阵列的读出放大器的信号。

8. 发明授权

US06313694B1 Internal power voltage generating circuit having a single drive transistor for stand-by and active modes 有权
标题翻译：具有用于待机模式和有源模式的单个驱动晶体管的内部电源电压发生电路
公开(公告)号：US06313694B1
公开(公告)日：2001-11-06
申请号：US09399925
申请日：1999-09-21
申请人： Kyo-Min Sohn
发明人： Kyo-Min Sohn
IPC分类号： G05F110
CPC分类号： G05F1/465
摘要： An internal power voltage generating circuit for a semiconductor device reduces current consumption during stand-by mode and allows a fast transition to active mode by using a single output driver for both standby mode and active mode. The output driver is coupled to both an active mode comparison circuit, which is disabled during stand-by-mode, and a stand-by mode comparison circuit which is enabled during stand-by-mode. The active mode comparison circuit is fabricated from large transistors and generates a first output signal having a high current capacity to turn the output driver completely on. The stand-by mode comparison circuit is fabricated from small transistors and generators a second output signal having a low current capacity which only turns the output driver partially on. The output driver can switch quickly from stand-by-mode to active mode because it is not turned completely off during stand-by-mode. This also eliminates the need for an additional circuit for turning the driver completely off. The stand-by-mode comparison circuit can by left on during active mode without influencing the output driver because the current capacity of its output signal is small compared to that of the active mode comparison circuit.
摘要翻译：用于半导体器件的内部电源电压产生电路在待机模式下降低了电流消耗，并且通过使用用于待机模式和主动模式的单个输出驱动器来快速转换到主动模式。输出驱动器耦合到在待机模式期间被禁用的有源模式比较电路和在待机模式期间被使能的待机模式比较电路。有源模式比较电路由大晶体管制成，并产生具有高电流容量的第一输出信号，以使输出驱动器完全导通。备用模式比较电路由小型晶体管和发生器制成具有低电流容量的第二输出信号，其仅部分打开输出驱动器。输出驱动器可以从待机模式切换到主动模式，因为它在待机模式下未完全关闭。这也消除了对完全关闭驱动器的附加电路的需要。待机模式比较电路可以在激活模式下保持开启，而不会影响输出驱动器，因为其输出信号的电流容量与有源模式比较电路相比较小。

9. 发明申请

US20160322085A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20160322085A1
公开(公告)日：2016-11-03
申请号：US15206106
申请日：2016-07-08
申请人： Kyo-min SOHN
发明人： Kyo-min SOHN
IPC分类号： G11C7/10 , G11C7/22 , G11C7/12
CPC分类号： G11C7/1009 , G11C5/02 , G11C5/06 , G11C7/1006 , G11C7/1045 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/1675 , G11C11/4085 , G11C11/4096 , G11C11/4097 , G11C2211/5647
摘要： A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

10. 发明申请

US20160163373A1 MEMORY DEVICE FOR CONTROLLING REFRESH OPERATION BY USING CELL CHARACTERISTIC FLAGS 审中-公开
标题翻译：通过使用细胞特征标记来控制刷新操作的存储器件
公开(公告)号：US20160163373A1
公开(公告)日：2016-06-09
申请号：US14956792
申请日：2015-12-02
申请人： Ki-ho HYUN , Kyo-min SOHN , Je-min RYU , Ho-Seok SEOL
发明人： Ki-ho HYUN , Kyo-min SOHN , Je-min RYU , Ho-Seok SEOL
IPC分类号： G11C11/406 , G11C11/4093 , G11C11/408
CPC分类号： G11C11/4087 , G11C11/40611 , G11C11/40622 , G11C11/4093 , G11C2211/4061
摘要： A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.
摘要翻译：存储器装置包括存储单元阵列，其包括多个存储单元行; 以及刷新地址生成器，其被配置为存储分别对应于所述多个存储单元行的标志，通过执行计数操作来生成分别对应于所述多个存储单元行的刷新行地址，并且根据所述标志，多个存储单元行。

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