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1. 发明授权

US07049232B2 Methods for forming ruthenium films with β-diketone containing ruthenium complexes and method for manufacturing metal-insulator-metal capacitor using the same 有权
公开(公告)号：US07049232B2
公开(公告)日：2006-05-23
申请号：US10657596
申请日：2003-09-08
申请人： Kwang-hee Lee , Cha-young Yoo , Han-jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
发明人： Kwang-hee Lee , Cha-young Yoo , Han-jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
IPC分类号： H01L21/44
CPC分类号： C23C16/18 , H01L21/28556 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2–1 ccm and oxygen at a flow rate of 20–60 sccm, and depositing the ruthenium film at a temperature of 330–430° C. under a pressure of 0.5–5 Torr using chemical vapor deposition (CVD).

2. 发明申请

US20060148193A1 Methods for forming ruthenium films with beta-diketone containing ruthenium complexes and method for manufacturing metal-insulator-metal capacitor using the same 审中-公开
标题翻译：用含有钌络合物的β-二酮形成钌膜的方法及使用其制造金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US20060148193A1
公开(公告)日：2006-07-06
申请号：US11374349
申请日：2006-03-13
申请人： Kwang-hee Lee , Cha-young Yoo , Han-Jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
发明人： Kwang-hee Lee , Cha-young Yoo , Han-Jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
IPC分类号： H01L21/44
CPC分类号： C23C16/18 , H01L21/28556 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2-1 ccm and oxygen at a flow rate of 20-60 sccm, and depositing the ruthenium film at a temperature of 330-430° C. under a pressure of 0.5-5 Torr using chemical vapor deposition (CVD).
摘要翻译：提供1）一种在单一工艺条件下形成钌膜的方法，由此保持钌膜对下层的高附着性，以及2）使用这种方法制造金属 - 绝缘体 - 金属（MIM）电容器的方法钌膜成型方法。形成钌膜的方法包括以0.2-1ccm的流速和20-60sccm的流量的氧供给双（异庚烷-2,4-二酮）降冰片二烯钌，并将钌膜以在0.5-5乇的压力下使用化学气相沉积（CVD）来制备330-430℃。

3. 发明授权

US06743678B2 Methods for manufacturing semiconductor memory devices 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US06743678B2
公开(公告)日：2004-06-01
申请号：US10424959
申请日：2003-04-28
申请人： Kwang-hee Lee , Sung-tae Kim , Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-hoon Oh
发明人： Kwang-hee Lee , Sung-tae Kim , Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-hoon Oh
IPC分类号： H01L21336
CPC分类号： H01L28/75 , H01L28/65
摘要： A lower electrode is formed from a first metal on a semiconductor substrate. Atoms of a second metal, that is different than the first metal, are diffused into the lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer. Diffusion of second metal atoms into the lower electrode may reduce or prevent crystal grain growth and agglomeration on a surface of the lower electrode during a subsequent high temperature process.
摘要翻译：下电极由半导体衬底上的第一金属形成。与第一金属不同的第二金属的原子被扩散到下电极中。在下电极上形成介电层，在电介质层上形成上电极。在随后的高温过程中，第二金属原子向下电极的扩散可以减少或防止下电极表面上的晶粒生长和结块。

4. 发明授权

US06995071B2 Methods of forming MIM type capacitor structures using low temperature plasma processing 有权
标题翻译：使用低温等离子体处理形成MIM型电容器结构的方法
公开(公告)号：US06995071B2
公开(公告)日：2006-02-07
申请号：US10830214
申请日：2004-04-22
申请人： Se-hoon Oh , Jung-hee Chung , Jae-hyoung Choi , Jeong-sik Choi , Sung-tae Kim , Cha-young Yoo
发明人： Se-hoon Oh , Jung-hee Chung , Jae-hyoung Choi , Jeong-sik Choi , Sung-tae Kim , Cha-young Yoo
IPC分类号： H10L21/8242
CPC分类号： H01L27/10852 , C23C16/405 , C23C16/56 , H01L21/02181 , H01L21/0228 , H01L21/0234 , H01L21/02356 , H01L21/31645 , H01L27/10817 , H01L27/10855 , H01L28/91 , Y10S438/957
摘要： Methods of forming metal-insulator-metal type capacitors in integrated circuit memory devices can include crystallizing an HfO2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in range between about 250 degrees Centigrade and about 450 degrees Centigrade. An upper electrode can be formed on the HfO2 dielectric layer.
摘要翻译：在集成电路存储器件中形成金属 - 绝缘体 - 金属型电容器的方法可以包括在低温等离子体处理中在电容器结构的下部电极上结晶HfO 2/2电介质层，温度范围为约250摄氏度和约450摄氏度。上电极可以形成在HfO 2 2电介质层上。

5. 发明授权

US07314806B2 Methods of forming metal-insulator-metal (MIM) capacitors with separate seed 有权
标题翻译：用分离的种子形成金属 - 绝缘体 - 金属（MIM）电容器的方法
公开(公告)号：US07314806B2
公开(公告)日：2008-01-01
申请号：US11097404
申请日：2005-04-01
申请人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
发明人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
IPC分类号： H01L21/20
CPC分类号： H01L21/31122
摘要： A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a metal-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
摘要翻译：可以在金属 - 绝缘体 - 金属（MIM）型电容器的金属氮化物下电极上形成金属 - 氮化物种子电介质层。金属 - 氮化物种子电介质层可以用作阻挡层，以在例如用于在包括MIM型的集成电路中形成上层金属化/结构的后端处理中减少与金属氮化物下电极的反应电容器。包含在金属 - 氮氧化物种子电介质层中的氮可以减少在常规型MIM电容器中可能发生的反应类型。可以在金属 - 氮化物种子介电层上形成金属氧化物主介电层，并且可以与MIM型电容器中的金属 - 氮化物种子电介质层保持分离。金属氧化物主电介质层可以被稳定（使用例如热或等离子体处理）以从其中去除缺陷（例如碳）并调整金属氧化物主介电层的化学计量。

6. 发明授权

US06680251B2 Methods of chemical vapor depositing ruthenium by varying chemical vapor deposition parameters 有权
标题翻译：通过改变化学气相沉积参数化学气相沉积钌的方法
公开(公告)号：US06680251B2
公开(公告)日：2004-01-20
申请号：US10080000
申请日：2002-02-21
申请人： Seok-jun Won , Cha-young Yoo , Sung-tae Kim , Young-wook Park , Yun-jung Lee , Soon-yeon Park
发明人： Seok-jun Won , Cha-young Yoo , Sung-tae Kim , Young-wook Park , Yun-jung Lee , Soon-yeon Park
IPC分类号： H01L2144
CPC分类号： H01L21/28556 , C23C16/0272 , C23C16/40 , H01L21/28568 , H01L28/55 , H01L28/60
摘要： A layer is formed by chemical vapor depositing a seeding layer of ruthenium oxide on a substrate at a chemical vapor deposition flow rate ratio of a ruthenium source to oxygen gas. A main layer of ruthenium is chemical vapor deposited on the seeding layer by increasing the chemical vapor deposition flow rate ratio of the ruthenium source to the oxygen gas.
摘要翻译：通过以钌源与氧气的化学气相沉积流速比在化学气相沉积基底上的氧化钌晶面层形成层。钌的主层通过提高钌源与氧气的化学气相沉积流速比化学气相沉积在接种层上。

7. 发明申请

US20050227432A1 Methods of forming metal-insulator-metal (MIM) capacitors with separate seed and main dielectric layers and MIM capacitors so formed 有权
标题翻译：形成金属 - 绝缘体 - 金属（MIM）电容器的方法，该电容器具有单独的种子和主电介质层以及如此形成的MIM电容器
公开(公告)号：US20050227432A1
公开(公告)日：2005-10-13
申请号：US11097404
申请日：2005-04-01
申请人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
发明人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
IPC分类号： H01L27/108 , H01L21/311 , H01L21/8242
CPC分类号： H01L21/31122
摘要： A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a meta-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
摘要翻译：可以在间绝缘子金属（MIM）型电容器的金属氮化物下电极上形成金属 - 氮氧化物种子电介质层。金属 - 氮化物种子电介质层可以用作阻挡层，以在例如用于在包括MIM型的集成电路中形成上层金属化/结构的后端处理中减少与金属氮化物下电极的反应电容器。包含在金属 - 氮氧化物种子电介质层中的氮可以减少在常规型MIM电容器中可能发生的反应类型。可以在金属 - 氮化物种子介电层上形成金属氧化物主介电层，并且可以与MIM型电容器中的金属 - 氮化物种子电介质层保持分离。金属氧化物主电介质层可以被稳定（使用例如热或等离子体处理）以从其中去除缺陷（例如碳）并调整金属氧化物主介电层的化学计量。

8. 发明授权

US06893501B2 Method for manufacturing a semiconductor device having a capping layer covering a capacitor of the semiconductor device 有权
标题翻译：一种具有覆盖半导体器件的电容器的覆盖层的半导体器件的制造方法
公开(公告)号：US06893501B2
公开(公告)日：2005-05-17
申请号：US10320407
申请日：2002-12-17
申请人： Ki-chul Kim , Sung-tae Kim , Young-sun Kim , Jeong-hee Chung , Wan-don Kim , Yun-jung Lee , Han-mei Choi
发明人： Ki-chul Kim , Sung-tae Kim , Young-sun Kim , Jeong-hee Chung , Wan-don Kim , Yun-jung Lee , Han-mei Choi
IPC分类号： H01L27/04 , H01L21/02 , H01L21/316 , H01L21/8242 , C30B25/04
CPC分类号： H01L28/57 , H01L21/02183 , H01L21/02271 , H01L21/02356 , H01L21/31637 , H01L27/1085 , H01L28/65
摘要： A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.
摘要翻译：一种覆盖半导体存储器件的电容器，优选金属 - 绝缘体 - 金属（MIM）电容器的覆盖层的方法，其中所述方法包括在半导体上形成具有下电极，电介质层和上电极的电容器衬底，在电容器上形成覆盖层，并使介电层结晶。这里，形成覆盖层包括在不提供氧气的情况下沉积封盖层的稳定性，通过为封盖层提供反应源沉积覆盖层; 并且清洗用于形成覆盖层的反应器的内部。

9. 发明授权

US07531861B2 Trench capacitors with insulating layer collars in undercut regions 失效
标题翻译：带有绝缘层的沟槽电容器在底切区域
公开(公告)号：US07531861B2
公开(公告)日：2009-05-12
申请号：US12033065
申请日：2008-02-19
申请人： Suk-jin Chung , Seung-hwan Lee , Sung-tae Kim , Young-sun Kim , Jae-soon Lim , Young-geun Park
发明人： Suk-jin Chung , Seung-hwan Lee , Sung-tae Kim , Young-sun Kim , Jae-soon Lim , Young-geun Park
IPC分类号： H01L29/94
CPC分类号： H01L27/10867 , H01L27/10829 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.
摘要翻译：提供了在底切区域中具有绝缘层套环的沟槽电容器和制造这种沟槽电容器的方法。制造沟槽电容器的一些方法包括在衬底上形成第一层。在与衬底相对的第一层上形成第二层。形成在第一和第二层的顶部上具有开口的掩模。通过从掩模中的开口去除第一层和第二层的一部分来形成第一沟槽。除去第二层下面的第一层的一部分，以在第二层下形成底切区域。在第二层下方的底切区域中形成绝缘层套环。形成第二沟槽，其通过从掩模中的开口去除衬底的一部分而从第一沟槽延伸。掩埋板沿着第二沟槽形成在衬底中。介电层形成在第二沟槽的内壁和底部上。在电介质层上的第二沟槽中形成存储电极。

10. 发明申请

US20080135876A1 TRENCH CAPACITORS WITH INSULATING LAYER COLLARS IN UNDERCUT REGIONS 失效
标题翻译：在内陆地区具有绝缘层的TRENCH电容器
公开(公告)号：US20080135876A1
公开(公告)日：2008-06-12
申请号：US12033065
申请日：2008-02-19
申请人： Suk-jin Chung , Seung-hwan Lee , Sung-tae Kim , Young-sun Kim , Jae-soon Lim , Young-geun Park
发明人： Suk-jin Chung , Seung-hwan Lee , Sung-tae Kim , Young-sun Kim , Jae-soon Lim , Young-geun Park
IPC分类号： H01L29/94
CPC分类号： H01L27/10867 , H01L27/10829 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.
摘要翻译：提供了在底切区域中具有绝缘层套环的沟槽电容器和制造这种沟槽电容器的方法。制造沟槽电容器的一些方法包括在衬底上形成第一层。在与衬底相对的第一层上形成第二层。形成在第一和第二层的顶部上具有开口的掩模。通过从掩模中的开口去除第一层和第二层的一部分来形成第一沟槽。除去第二层下面的第一层的一部分，以在第二层下形成底切区域。在第二层下方的底切区域中形成绝缘层套环。形成第二沟槽，其通过从掩模中的开口去除衬底的一部分而从第一沟槽延伸。掩埋板沿着第二沟槽形成在衬底中。介电层形成在第二沟槽的内壁和底部上。在电介质层上的第二沟槽中形成存储电极。

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