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1. 发明申请

US20080291753A1 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US20080291753A1
公开(公告)日：2008-11-27
申请号：US12219816
申请日：2008-07-29
申请人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

2. 发明授权

US07453745B2 Semiconductor memory device and latency signal generating method thereof 有权
公开(公告)号：US07453745B2
公开(公告)日：2008-11-18
申请号：US11416077
申请日：2006-05-03
申请人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

3. 发明申请

US20100271886A1 Semiconductor memory device and latency signal generating method thereof 审中-公开
公开(公告)号：US20100271886A1
公开(公告)日：2010-10-28
申请号：US12801953
申请日：2010-07-02
申请人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

4. 发明授权

US07778094B2 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US07778094B2
公开(公告)日：2010-08-17
申请号：US12219816
申请日：2008-07-29
申请人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

5. 发明申请

US20060250861A1 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US20060250861A1
公开(公告)日：2006-11-09
申请号：US11416077
申请日：2006-05-03
申请人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

6. 发明申请

US20110246857A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20110246857A1
公开(公告)日：2011-10-06
申请号：US13078364
申请日：2011-04-01
申请人： Seung-Jun Bae , Kwang-Il Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-Il Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： H03M13/09 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

7. 发明授权

US07366822B2 Semiconductor memory device capable of reading and writing data at the same time 有权
标题翻译：能够同时读取和写入数据的半导体存储器件
公开(公告)号：US07366822B2
公开(公告)日：2008-04-29
申请号：US10840268
申请日：2004-05-07
申请人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
发明人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
IPC分类号： G06F12/00 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1072 , G11C11/4082 , G11C11/4087
摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.
摘要翻译：半导体存储器件包括多个存储体。数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少。

8. 发明授权

US5640354A Dynamic random access memory having self-test function 失效
标题翻译：具有自检功能的动态随机存取存储器
公开(公告)号：US5640354A
公开(公告)日：1997-06-17
申请号：US636003
申请日：1996-04-22
申请人： Seong Jin Jang , Young-Hyun Jun , Jae Sik Lee
发明人： Seong Jin Jang , Young-Hyun Jun , Jae Sik Lee
IPC分类号： G11C29/00 , G11C11/401 , G11C11/407 , G11C29/12 , G11C29/44 , G11C29/46 , G11C11/34
CPC分类号： G11C29/46 , G11C29/44
摘要： An improved DRAM having a self-test function capable of performing a self-test function in a fast page mode in accordance with a transition of a column address in accordance with an interior clock signal without a toggle of a column address strobe signal, which includes an entry/exit control unit for generating a self-test entry signal in accordance with a combination a predetermined address signal and an external synchronous signal; a signal transition detection unit for detecting a transition of a self-test entry signal and a word line enable signal and for outputting a transition detection signal; a counter for counting an interior clock signal outputted in accordance with a transition detection signal; a data generating and comparison unit for writing and reading a test data without a toggle of the external synchronous signal comparing the read test data with the generated test data; and an error and end detection unit for generating an error flag and end flag.
摘要翻译：一种具有自检功能的改进DRAM，其能够根据内部时钟信号而根据列地址的转换而在快速页模式下执行自检功能，而不需要列地址选通信号的切换，该DRAM地址选通信号包括入口/出口控制单元，用于根据预定地址信号和外部同步信号的组合产生自检入口信号; 信号转换检测单元，用于检测自检入场信号和字线使能信号的转变，并输出转换检测信号; 计数器，用于对根据转换检测信号输出的内部时钟信号进行计数; 数据生成和比较单元，用于在不读取测试数据与所生成的测试数据的外部同步信号的切换的情况下写入和读取测试数据; 以及用于产生错误标志和结束标志的错误和结束检测单元。

9. 发明授权

US07092299B2 Memory devices, systems and methods using selective on-die termination 有权
标题翻译：存储器件，系统和使用选择性片上端接的方法
公开(公告)号：US07092299B2
公开(公告)日：2006-08-15
申请号：US10792623
申请日：2004-03-03
申请人： Jin-Seok Kwak , Seong-Jin Jang , Young-Hyun Jun
发明人： Jin-Seok Kwak , Seong-Jin Jang , Young-Hyun Jun
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/10 , G11C7/1048
摘要： A memory system includes first and second memory devices having commonly connected data terminals and commonly connected memory control signal terminals, e.g., devices in respective first and second independently selectable memory banks that share common data lines and common memory control signal lines, such as column address strobe, row address strobe, write enable, and address signal lines. The first and second memory devices includes respective selective on-die termination (ODT) circuits configured to selectively provide first and second termination impedances at their respective data terminals responsive to a memory control signal at the commonly connected memory control signal terminals. The selective ODT circuits may produce the first termination impedance responsive to a memory write operation, and may produce the second termination impedance responsive to a memory read operation and/or expiration of a predetermined time interval following termination of the memory write operation. Preferably, the first termination impedance is less than the second termination impedance, and the selective ODT circuits provide the first termination impedance responsive to the memory write operation irrespective of which of the first and second memory devices is being written to.
摘要翻译：存储器系统包括具有共同连接的数据端子和共同连接的存储器控制信号端子的第一和第二存储器件，例如共享公共数据线和公共存储器控制信号线的各自的第一和第二可独立选择的存储体中的器件，诸如列地址选通，行地址选通，写使能和地址信号线。第一和第二存储器件包括相应的选择性管芯端接（ODT）电路，其被配置为响应于在共同连接的存储器控制信号端子处的存储器控制信号在它们各自的数据端口选择性地提供第一和第二终端阻抗。响应于存储器写入操作，选择性ODT电路可以产生第一终止阻抗，并且可以在存储器写入操作终止之后响应于存储器读取操作和/或预定时间间隔的期满而产生第二终止阻抗。优选地，第一终端阻抗小于第二终端阻抗，并且选择性ODT电路响应于存储器写入操作提供第一终止阻抗，而与正在写入的第一和第二存储器件中的哪一个无关。

10. 发明授权

US06653889B2 Voltage generating circuits and methods including shared capacitors 失效
标题翻译：电压产生电路和方法包括共享电容
公开(公告)号：US06653889B2
公开(公告)日：2003-11-25
申请号：US10188927
申请日：2002-07-02
申请人： Seong-Jin Jang , Young-Hyun Jun
发明人： Seong-Jin Jang , Young-Hyun Jun
IPC分类号： G05F110
CPC分类号： G11C5/145 , H02M3/073
摘要： Integrated circuit voltage generating circuits include an integrated circuit substrate, a first voltage generating circuit in the integrated substrate that is configured to generate a first voltage from a power supply voltage, and a second voltage generating circuit in the integrated circuit substrate that is configured to generate a second voltage that is different from the first voltage from the power supply voltage. A shared capacitor in the integrated circuit substrate is connected to both the first voltage generating circuit and to the second voltage generating circuit. The shared capacitor is used by the first voltage generating circuit and the second voltage generating circuit, to generate the first and second voltages.
摘要翻译：集成电路电压产生电路包括集成电路基板，被配置为从电源电压产生第一电压的集成基板中的第一电压产生电路，以及集成电路基板中的第二电压产生电路，其被配置为产生与电源电压的第一电压不同的第二电压。集成电路基板中的共用电容器连接到第一电压产生电路和第二电压产生电路。共享电容器由第一电压产生电路和第二电压产生电路用于产生第一和第二电压。

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