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1. 发明授权

US06638838B1 Semiconductor structure including a partially annealed layer and method of forming the same 失效
标题翻译：包括部分退火层的半导体结构及其形成方法
公开(公告)号：US06638838B1
公开(公告)日：2003-10-28
申请号：US09678372
申请日：2000-10-02
申请人： Kurt Eisenbeiser , Barbara M. Foley , Jeffrey M. Finder , Danny L. Thompson
发明人： Kurt Eisenbeiser , Barbara M. Foley , Jeffrey M. Finder , Danny L. Thompson
IPC分类号： H01L2120
CPC分类号： H01L21/02521 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02505 , H01L21/0251
摘要： High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. To further relieve strain in the accommodating buffer layer, at least a portion of the accommodating buffer layer is exposed to a laser anneal process to cause the accommodating buffer layer to become amorphous, providing a true compliant substrate for subsequent layer growth.
摘要翻译：通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。容纳缓冲层与下面的硅晶片和上覆的单晶化合物半导体层晶格匹配。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。为了进一步减轻容纳缓冲层中的应变，容纳缓冲层的至少一部分暴露于激光退火工艺，以使得容纳缓冲层变得非晶体，为随后的层生长提供真正的柔性衬底。

2. 发明授权

US06750067B2 Microelectronic piezoelectric structure and method of forming the same 失效
标题翻译：微电子压电结构及其形成方法
公开(公告)号：US06750067B2
公开(公告)日：2004-06-15
申请号：US10126772
申请日：2002-04-19
申请人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
发明人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
IPC分类号： H01L2100
CPC分类号： B32B9/00 , H01L21/31691 , H01L28/56 , H01L41/0478 , H01L41/0815 , H01L41/1876 , H01L41/319
摘要： A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.
摘要翻译：通过首先在硅晶片上生长钛酸锶层，可以将大量的单晶Pb（Zr，Ti）O 3的高品质外延层生长在大的硅晶片上。钛酸锶层是通过硅氧化物的非晶界面层与硅晶片隔开的单晶层。

3. 发明授权

US06482538B2 Microelectronic piezoelectric structure and method of forming the same 失效
标题翻译：微电子压电结构及其形成方法
公开(公告)号：US06482538B2
公开(公告)日：2002-11-19
申请号：US09912994
申请日：2001-07-25
申请人： Ramamoorthy Ramesh , Yu Wang , Jeffrey M. Finder , Zhiyi Yu , Ravindranath Droopad , Kurt Eisenbeiser
发明人： Ramamoorthy Ramesh , Yu Wang , Jeffrey M. Finder , Zhiyi Yu , Ravindranath Droopad , Kurt Eisenbeiser
IPC分类号： B32B1900
CPC分类号： H01L21/02197 , B32B9/00 , H01L21/02293 , H01L21/31691 , H01L28/56 , H01L41/0478 , H01L41/1875 , H01L41/1876 , H01L41/29 , H01L41/319 , Y10T428/24917
摘要： A high quality epitaxial layer of monocrystalline Pb(Mg,Nb)O3—PbTiO3 or Pb(Mg1−xNbx)O3—PbTiO3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.
摘要翻译：首先在硅晶片上生长钛酸锶层，可以将大量的单晶Pb（Mg，Nb）O3-PbTiO3或Pb（Mg1-xNbx）O3-PbTiO3）的高质量外延层生长在大的硅晶片上。钛酸锶层是通过硅氧化物的非晶界面层与硅晶片隔开的单晶层。

4. 发明授权

US06555946B1 Acoustic wave device and process for forming the same 失效
标题翻译：声波装置及其形成方法
公开(公告)号：US06555946B1
公开(公告)日：2003-04-29
申请号：US09624803
申请日：2000-07-24
申请人： Jeffrey M. Finder , Kurt Eisenbeiser , Jamal Ramdani , Ravindranath Droopad , William Jay Ooms
发明人： Jeffrey M. Finder , Kurt Eisenbeiser , Jamal Ramdani , Ravindranath Droopad , William Jay Ooms
IPC分类号： H01L4108
CPC分类号： H03H9/174 , H01L27/20 , H01L41/319 , H03H3/02 , H03H3/08 , H03H9/02574 , H03H9/0542
摘要： High quality epitaxial layers of piezoelectric material materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
摘要翻译：通过首先在硅晶片上生长一个容纳缓冲层，可以将高质量的压电材料外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

5. 发明授权

US06365474B1 Method of fabricating an integrated circuit 有权
标题翻译：制造集成电路的方法
公开(公告)号：US06365474B1
公开(公告)日：2002-04-02
申请号：US09599697
申请日：2000-06-22
申请人： Jeffrey M. Finder , Kurt Eisenbeiser , Bich-Yen Nguyen
发明人： Jeffrey M. Finder , Kurt Eisenbeiser , Bich-Yen Nguyen
IPC分类号： H01L21336
CPC分类号： H01L29/66545
摘要： A transistor (12) and method of making an integrated circuit (10) uses a chromium based sacrificial gate (22A) to align, dope and activate source and drain portions (36, 38, 52, 53,) of the transistor. The transistor is subjected to a high temperature to activate the source and drain, which would damage a high permittivity gate dielectric. The sacrificial gate is removed by etching with ceric ammonia nitrate. A high permittivity gate dielectric (72) and a final gate electrode (74) are formed over a channel (30) of the transistor. Electrodes (76, 78) are formed for coupling to the source and drain.
摘要翻译：晶体管（12）和制造集成电路（10）的方法使用铬基牺牲栅极（22A）来对准，掺杂并激活晶体管的源极和漏极部分（36,38,52,53）。晶体管经受高温以激活源极和漏极，这将损坏高介电常数栅极电介质。通过用硝酸铈铵蚀刻除去牺牲栅极。在晶体管的沟道（30）上形成高介电常数栅极电介质（72）和最终栅电极（74）。电极（76,78）形成为用于耦合到源极和漏极。

6. 发明授权

US06432546B1 Microelectronic piezoelectric structure and method of forming the same 失效
标题翻译：微电子压电结构及其形成方法
公开(公告)号：US06432546B1
公开(公告)日：2002-08-13
申请号：US09624527
申请日：2000-07-24
申请人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
发明人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
IPC分类号： B32B900
CPC分类号： B32B9/00 , H01L21/31691 , H01L28/56 , H01L41/0478 , H01L41/0815 , H01L41/1876 , H01L41/319
摘要： A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.
摘要翻译：通过首先在硅晶片上生长钛酸锶层，可以将大量的单晶Pb（Zr，Ti）O 3的高品质外延层生长在大的硅晶片上。钛酸锶层是通过硅氧化物的非晶界面层与硅晶片隔开的单晶层。

7. 发明申请

US20120214047A1 METHOD FOR HIGH VOLUME MANUFACTURING OF THIN FILM BATTERIES 审中-公开
标题翻译：薄膜电池高容量制造方法
公开(公告)号：US20120214047A1
公开(公告)日：2012-08-23
申请号：US13461286
申请日：2012-05-01
申请人： BYUNG SUNG KWAK , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
发明人： BYUNG SUNG KWAK , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
IPC分类号： H01M4/70 , H01M2/02
CPC分类号： H01M10/0585 , H01M6/40 , H01M10/0436 , H01M10/052 , H01M2300/0068
摘要： Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.
摘要翻译：提供了概念和方法，以通过消除和/或最小化常规物理（阴影）掩模的使用来降低薄膜电池（TFB）大批量制造的成本和复杂性。激光划线和其他可选的物理无掩模图案化技术满足某些或所有图案化要求。在一个实施例中，制造薄膜电池的方法包括提供衬底，在衬底上沉积与薄膜电池结构相对应的层，所述层按沉积顺序包括阴极，电解质和阳极，其中至少沉积层中的一个在沉积期间由物理掩模未图案化，沉积保护涂层，以及划刻层和保护涂层。此外，层的边缘可以被封装层覆盖。此外，可以将这些层沉积在两个基板上，然后层压以形成薄膜电池。

8. 发明授权

US6091621A Non-volatile multistate memory cell using a ferroelectric gate fet 失效
标题翻译：使用铁电栅极的非易失性多态存储单元
公开(公告)号：US6091621A
公开(公告)日：2000-07-18
申请号：US985456
申请日：1997-12-05
申请人： Yang Wang , Jenn-Hwa Huang , Kurt Eisenbeiser , Ellen Lan , William J. Ooms
发明人： Yang Wang , Jenn-Hwa Huang , Kurt Eisenbeiser , Ellen Lan , William J. Ooms
IPC分类号： G11C11/22 , G11C11/56
CPC分类号： G11C11/22 , G11C11/5657
摘要： A multi-state non-volatile ferroelectric memory includes a field effect transistor having a gate insulator formed of ferroelectric material. The ferroelectric material is separated into regions of different characteristics, e.g. different thicknesses, different coercive field values, etc., so as to provide a plurality of different threshold voltages for the field effect transistor.
摘要翻译：多状态非易失性铁电存储器包括具有由铁电材料形成的栅极绝缘体的场效应晶体管。铁电材料被分成不同特性的区域，例如不同的厚度，不同的矫顽场值等，以便为场效应晶体管提供多个不同的阈值电压。

9. 发明授权

US08168318B2 Method for high volume manufacturing of thin film batteries 有权
标题翻译：薄膜电池大批量生产方法
公开(公告)号：US08168318B2
公开(公告)日：2012-05-01
申请号：US12257049
申请日：2008-10-23
申请人： Byung Sung Kwak , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
发明人： Byung Sung Kwak , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
IPC分类号： H01M6/16 , H01M6/18 , H01M6/46
CPC分类号： H01M10/0585 , H01M6/40 , H01M10/0436 , H01M10/052 , H01M2300/0068
摘要： Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.
摘要翻译：提供了概念和方法，以通过消除和/或最小化常规物理（阴影）掩模的使用来降低薄膜电池（TFB）大批量制造的成本和复杂性。激光划线和其他可选的物理无掩模图案化技术满足某些或所有图案化要求。在一个实施例中，制造薄膜电池的方法包括提供衬底，在衬底上沉积与薄膜电池结构相对应的层，所述层按沉积顺序包括阴极，电解质和阳极，其中至少沉积层中的一个在沉积期间由物理掩模未图案化，沉积保护涂层，以及划刻层和保护涂层。此外，层的边缘可以被封装层覆盖。此外，可以将这些层沉积在两个基板上，然后层压以形成薄膜电池。

10. 发明申请

US20050056210A1 Heterojunction tunneling diodes and process for fabricating same 有权
标题翻译：异质结隧道二极管及其制造方法
公开(公告)号：US20050056210A1
公开(公告)日：2005-03-17
申请号：US10911624
申请日：2004-08-05
申请人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
发明人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
IPC分类号： H01L21/20 , H01L21/8258 , H01L27/06 , H01L29/88 , C30B1/00 , C30B3/00 , C30B5/00 , C30B23/00 , C30B25/00 , C30B28/02 , C30B28/12 , C30B28/14
CPC分类号： H01L29/882 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02505 , H01L21/02521 , H01L21/8258 , H01L27/0605
摘要： High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
摘要翻译：通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

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