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1. 发明申请

US20120214047A1 METHOD FOR HIGH VOLUME MANUFACTURING OF THIN FILM BATTERIES 审中-公开
标题翻译：薄膜电池高容量制造方法
公开(公告)号：US20120214047A1
公开(公告)日：2012-08-23
申请号：US13461286
申请日：2012-05-01
申请人： BYUNG SUNG KWAK , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
发明人： BYUNG SUNG KWAK , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
IPC分类号： H01M4/70 , H01M2/02
CPC分类号： H01M10/0585 , H01M6/40 , H01M10/0436 , H01M10/052 , H01M2300/0068
摘要： Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.
摘要翻译：提供了概念和方法，以通过消除和/或最小化常规物理（阴影）掩模的使用来降低薄膜电池（TFB）大批量制造的成本和复杂性。激光划线和其他可选的物理无掩模图案化技术满足某些或所有图案化要求。在一个实施例中，制造薄膜电池的方法包括提供衬底，在衬底上沉积与薄膜电池结构相对应的层，所述层按沉积顺序包括阴极，电解质和阳极，其中至少沉积层中的一个在沉积期间由物理掩模未图案化，沉积保护涂层，以及划刻层和保护涂层。此外，层的边缘可以被封装层覆盖。此外，可以将这些层沉积在两个基板上，然后层压以形成薄膜电池。

2. 发明授权

US08168318B2 Method for high volume manufacturing of thin film batteries 有权
标题翻译：薄膜电池大批量生产方法
公开(公告)号：US08168318B2
公开(公告)日：2012-05-01
申请号：US12257049
申请日：2008-10-23
申请人： Byung Sung Kwak , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
发明人： Byung Sung Kwak , Nety M. Krishna , Kurt Eisenbeiser , William J. Dauksher , Jon Candelaria
IPC分类号： H01M6/16 , H01M6/18 , H01M6/46
CPC分类号： H01M10/0585 , H01M6/40 , H01M10/0436 , H01M10/052 , H01M2300/0068
摘要： Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.
摘要翻译：提供了概念和方法，以通过消除和/或最小化常规物理（阴影）掩模的使用来降低薄膜电池（TFB）大批量制造的成本和复杂性。激光划线和其他可选的物理无掩模图案化技术满足某些或所有图案化要求。在一个实施例中，制造薄膜电池的方法包括提供衬底，在衬底上沉积与薄膜电池结构相对应的层，所述层按沉积顺序包括阴极，电解质和阳极，其中至少沉积层中的一个在沉积期间由物理掩模未图案化，沉积保护涂层，以及划刻层和保护涂层。此外，层的边缘可以被封装层覆盖。此外，可以将这些层沉积在两个基板上，然后层压以形成薄膜电池。

3. 发明授权

US6091621A Non-volatile multistate memory cell using a ferroelectric gate fet 失效
标题翻译：使用铁电栅极的非易失性多态存储单元
公开(公告)号：US6091621A
公开(公告)日：2000-07-18
申请号：US985456
申请日：1997-12-05
申请人： Yang Wang , Jenn-Hwa Huang , Kurt Eisenbeiser , Ellen Lan , William J. Ooms
发明人： Yang Wang , Jenn-Hwa Huang , Kurt Eisenbeiser , Ellen Lan , William J. Ooms
IPC分类号： G11C11/22 , G11C11/56
CPC分类号： G11C11/22 , G11C11/5657
摘要： A multi-state non-volatile ferroelectric memory includes a field effect transistor having a gate insulator formed of ferroelectric material. The ferroelectric material is separated into regions of different characteristics, e.g. different thicknesses, different coercive field values, etc., so as to provide a plurality of different threshold voltages for the field effect transistor.
摘要翻译：多状态非易失性铁电存储器包括具有由铁电材料形成的栅极绝缘体的场效应晶体管。铁电材料被分成不同特性的区域，例如不同的厚度，不同的矫顽场值等，以便为场效应晶体管提供多个不同的阈值电压。

4. 发明授权

US07105866B2 Heterojunction tunneling diodes and process for fabricating same 有权
标题翻译：异质结隧道二极管及其制造方法
公开(公告)号：US07105866B2
公开(公告)日：2006-09-12
申请号：US10911624
申请日：2004-08-05
申请人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
发明人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
IPC分类号： H01L29/861
CPC分类号： H01L29/882 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02505 , H01L21/02521 , H01L21/8258 , H01L27/0605
摘要： High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
摘要翻译：通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

5. 发明授权

US06432546B1 Microelectronic piezoelectric structure and method of forming the same 失效
标题翻译：微电子压电结构及其形成方法
公开(公告)号：US06432546B1
公开(公告)日：2002-08-13
申请号：US09624527
申请日：2000-07-24
申请人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
发明人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
IPC分类号： B32B900
CPC分类号： B32B9/00 , H01L21/31691 , H01L28/56 , H01L41/0478 , H01L41/0815 , H01L41/1876 , H01L41/319
摘要： A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.
摘要翻译：通过首先在硅晶片上生长钛酸锶层，可以将大量的单晶Pb（Zr，Ti）O 3的高品质外延层生长在大的硅晶片上。钛酸锶层是通过硅氧化物的非晶界面层与硅晶片隔开的单晶层。

6. 发明授权

US06309918B1 Manufacturable GaAs VFET process 失效
标题翻译：可制造的GaAs VFET工艺
公开(公告)号：US06309918B1
公开(公告)日：2001-10-30
申请号：US09157430
申请日：1998-09-21
申请人： Jenn-Hwa Huang , Benjamin W. Gable , Kurt Eisenbeiser , David Rhine
发明人： Jenn-Hwa Huang , Benjamin W. Gable , Kurt Eisenbeiser , David Rhine
IPC分类号： H01L21338
CPC分类号： H01L29/66856 , H01L29/8122 , Y10S438/945
摘要： A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.
摘要翻译：可制造的GaAs VFET工艺包括在其上提供掺杂的GaAs衬底和其上的轻掺杂的第一外延层和位于第一外延层上的重掺杂的第二外延层。耐温导电层定位在第二外延层上并且被图案化以限定多个细长的间隔开的源极区域。使用图案化的导电层，多个栅极沟槽被蚀刻到与源极区域相邻的第一外延层中。栅极沟槽的底部被植入和激活以形成栅极区域。栅极接触被沉积成与植入的栅极区域连通，源极接触层沉积成与覆盖在源极区域上的图案化导电层连通，并且漏极接触沉积在衬底的后表面上。

7. 发明授权

US5856684A High power HFET with improved channel interfaces 失效
标题翻译：大功率HFET，具有改进的通道接口
公开(公告)号：US5856684A
公开(公告)日：1999-01-05
申请号：US712760
申请日：1996-09-12
申请人： Yang Wang , Majid M. Hashemi , Kurt Eisenbeiser , Jenn-Hwa Huang
发明人： Yang Wang , Majid M. Hashemi , Kurt Eisenbeiser , Jenn-Hwa Huang
IPC分类号： H01L29/80 , H01L31/0328
CPC分类号： H01L29/802
摘要： A high power heterojunction field effect transistor comprising a first barrier layer including a semiconductor material having a band gap, a second barrier layer including a semiconductor material having a band gap, a channel layer including a semiconductor material having a band gap narrower than the band gaps of the material included in the first barrier layer and the second barrier layer and sandwiched therebetween and an interface layer sandwiched between the channel layer and the first barrier layer.
摘要翻译：一种高功率异质结场效应晶体管，包括：第一阻挡层，包括具有带隙的半导体材料;第二阻挡层，包括具有带隙的半导体材料;沟道层，包括具有比带隙窄的带隙的半导体材料包含在第一阻挡层和第二阻挡层中并夹在其间的材料以及夹在沟道层和第一阻挡层之间的界面层。

8. 发明申请

US20050056210A1 Heterojunction tunneling diodes and process for fabricating same 有权
标题翻译：异质结隧道二极管及其制造方法
公开(公告)号：US20050056210A1
公开(公告)日：2005-03-17
申请号：US10911624
申请日：2004-08-05
申请人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
发明人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
IPC分类号： H01L21/20 , H01L21/8258 , H01L27/06 , H01L29/88 , C30B1/00 , C30B3/00 , C30B5/00 , C30B23/00 , C30B25/00 , C30B28/02 , C30B28/12 , C30B28/14
CPC分类号： H01L29/882 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02505 , H01L21/02521 , H01L21/8258 , H01L27/0605
摘要： High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
摘要翻译：通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

9. 发明授权

US06750067B2 Microelectronic piezoelectric structure and method of forming the same 失效
标题翻译：微电子压电结构及其形成方法
公开(公告)号：US06750067B2
公开(公告)日：2004-06-15
申请号：US10126772
申请日：2002-04-19
申请人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
发明人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
IPC分类号： H01L2100
CPC分类号： B32B9/00 , H01L21/31691 , H01L28/56 , H01L41/0478 , H01L41/0815 , H01L41/1876 , H01L41/319
摘要： A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.
摘要翻译：通过首先在硅晶片上生长钛酸锶层，可以将大量的单晶Pb（Zr，Ti）O 3的高品质外延层生长在大的硅晶片上。钛酸锶层是通过硅氧化物的非晶界面层与硅晶片隔开的单晶层。

10. 发明授权

US06590236B1 Semiconductor structure for use with high-frequency signals 失效
标题翻译：用于高频信号的半导体结构
公开(公告)号：US06590236B1
公开(公告)日：2003-07-08
申请号：US09624296
申请日：2000-07-24
申请人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
发明人： Nada El-Zein , Jamal Ramdani , Kurt Eisenbeiser , Ravindranath Droopad
IPC分类号： H01L310328
CPC分类号： H01L21/31691 , C30B25/18 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02505 , H01L21/02521 , Y10S438/90 , Y10S438/933
摘要： High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. These semiconductor materials have applications involving communications with high frequency signals including intelligent transportation systems such as automobile radar systems, smart cruise control systems, collision avoidance systems, and automotive navigation systems; and electronic payment systems that use microwave or RF signals such as electronic toll payment for various transportation systems including train fares, and toll roads, parking structures, and toll bridges for automobiles.
摘要翻译：通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。这些半导体材料具有涉及与高频信号通信的应用，包括诸如汽车雷达系统，智能巡航控制系统，防撞系统和汽车导航系统之类的智能交通系统; 以及使用微波或RF信号的电子支付系统，例如用于包括火车票价的各种交通系统的电子费用付费，以及用于汽车的收费公路，停车场和收费桥。

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