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1. 发明授权

US08079002B1 Method and apparatus for evaluating paths in an integrated circuit design 有权
标题翻译：用于评估集成电路设计中的路径的方法和装置
公开(公告)号：US08079002B1
公开(公告)日：2011-12-13
申请号：US12344030
申请日：2008-12-24
申请人： Kuok-Khian Lo , Mark B. Roberts , Mohammed Fakhruddin , James Karp , Richard P. Burnley , Min-Hsing Chen
发明人： Kuok-Khian Lo , Mark B. Roberts , Mohammed Fakhruddin , James Karp , Richard P. Burnley , Min-Hsing Chen
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5054
摘要： An embodiment of the invention involves: providing a database that includes layout information representing a layout within an integrated circuit of an electrical circuit; identifying from the information in the database each conductive path of a selected type in the electrical circuit; extracting layout information from the database for each conductive path of the selected type; and calculating an electrical parameter for each conductive path of the selected type, as a function of the layout information obtained for that conductive path during the extracting. In addition, in a different configuration of the embodiment, a report can be generated containing information based on the electrical parameter calculated during the calculating for at least one of the conductive paths of the selected type.
摘要翻译：本发明的一个实施例涉及：提供包括表示电路集成电路内的布局的布局信息的数据库; 从数据库中的信息中识别电路中所选类型的每个导电路径; 从所述数据库中提取所选类型的每个导电路径的布局信息; 以及根据在提取期间为该导电路径获得的布局信息来计算所选类型的每个导电路径的电参数。此外，在本实施例的不同配置中，可以生成包含基于在所选择的类型的至少一个导电路径的计算期间计算的电参数的信息的报告。

2. 发明授权

US08982581B2 Electro-static discharge protection for die of a multi-chip module 有权
标题翻译：多芯片模块芯片的静电放电保护
公开(公告)号：US08982581B2
公开(公告)日：2015-03-17
申请号：US12828007
申请日：2010-06-30
申请人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
发明人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
IPC分类号： H05K7/00 , H01R43/00 , H01L23/60 , H01L25/065 , H01L27/02
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0255 , H01L2224/16225 , H01L2224/73253 , H01L2225/06572 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/19107 , Y10T29/49117
摘要： Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.
摘要翻译：描述了用于多芯片模块的管芯的静电放电（“ESD”）保护。在形成模具之后并且在组装多芯片模块之前，触点具有外部暴露的表面。该接触是用于多芯片模块的管芯到管芯互连。联系人是组装多芯片模块后的多芯片模块的内部节点。驱动器电路耦合到触点并且具有第一输入阻抗。放电电路耦合到触点用于驱动电路的静电放电保护，并且具有与第一放电路径相关联的第一正向偏置阻抗。第一个正向偏置阻抗是第一个输入阻抗的一小部分。

3. 发明授权

US08134813B2 Method and apparatus to reduce footprint of ESD protection within an integrated circuit 有权
标题翻译：降低集成电路内ESD保护占地面积的方法和装置
公开(公告)号：US08134813B2
公开(公告)日：2012-03-13
申请号：US12362471
申请日：2009-01-29
申请人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
发明人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.
摘要翻译：输入/输出（“I / O”）电路具有用硅化物块耦合到输入引脚的第一N沟道金属氧化物半导体（“NMOS”）场效应晶体管（“FET”）。第一P沟道金属氧化物半导体（“PMOS”）FET直接连接到输入引脚，其N阱电耦合到ESD阱偏置电路。 NMOS低压差分信号（“LVDS”）驱动器也直接连接到输入引脚，并具有级联的NMOS FET。 LVDS驱动器的第一个NMOS FET制造在电耦合到地的第一P抽头保护环和耦合到ESD阱偏置的N阱保护环上。 LVDS驱动器的第二个NMOS FET在与地耦合的第二个P分接保护环内制造。

4. 发明申请

US20120002392A1 ELECTRO-STATIC DISCHARGE PROTECTION FOR DIE OF A MULTI-CHIP MODULE 有权
标题翻译：多芯片模块电子放电放电保护
公开(公告)号：US20120002392A1
公开(公告)日：2012-01-05
申请号：US12828007
申请日：2010-06-30
申请人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
发明人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
IPC分类号： H05K7/00 , H01R43/00
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0255 , H01L2224/16225 , H01L2224/73253 , H01L2225/06572 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/19107 , Y10T29/49117
摘要： Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.
摘要翻译：描述了用于多芯片模块的管芯的静电放电（“ESD”）保护。在形成模具之后并且在组装多芯片模块之前，触点具有外部暴露的表面。该接触是用于多芯片模块的管芯到管芯互连。联系人是组装多芯片模块后的多芯片模块的内部节点。驱动器电路耦合到触点并且具有第一输入阻抗。放电电路耦合到触点用于驱动电路的静电放电保护，并且具有与第一放电路径相关联的第一正向偏置阻抗。第一个正向偏置阻抗是第一个输入阻抗的一小部分。

5. 发明授权

US08881085B1 Cell-level electrostatic discharge protection for an integrated circuit 有权
标题翻译：集成电路的电池级静电放电保护
公开(公告)号：US08881085B1
公开(公告)日：2014-11-04
申请号：US12793584
申请日：2010-06-03
申请人： James Karp , Greg W. Starr , Mohammed Fakhruddin
发明人： James Karp , Greg W. Starr , Mohammed Fakhruddin
IPC分类号： G06F17/50 , G06F7/38 , H01L25/00
CPC分类号： H01L27/0248 , G06F17/5081 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.
摘要翻译：评估用于静电放电（ESD）保护的布局单元的方法可以包括识别用于实现集成电路（IC）的布局单元的至少一个特征，并将布局单元的至少一个特征与ESD要求进行比较为IC。该方法可以包括指示布局单元的特征是否符合ESD要求。

6. 发明授权

US08866229B1 Semiconductor structure for an electrostatic discharge protection circuit 有权
标题翻译：一种静电放电保护电路的半导体结构
公开(公告)号：US08866229B1
公开(公告)日：2014-10-21
申请号：US13245162
申请日：2011-09-26
申请人： Mohammed Fakhruddin , James Karp
发明人： Mohammed Fakhruddin , James Karp
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of a semiconductor structure for an electrostatic discharge (“ESD”) protection circuit is disclosed. For this embodiment, there is a substrate of a first polarity type. A device area of the substrate has a source region and a drain region of a transistor. The device area is of the first polarity type, and the source region and the drain region are each of a second polarity type. A well region of the second polarity type surrounds the device area. An outer tap of the first polarity type surrounds the well region, and a bridge interconnects the source region and the outer tap.
摘要翻译：公开了一种用于静电放电（“ESD”）保护电路的半导体结构的实施例。对于该实施例，存在第一极性类型的衬底。衬底的器件区域具有晶体管的源极区域和漏极区域。器件区域是第一极性类型，源极区域和漏极区域分别是第二极性类型。第二极性类型的阱区围绕器件区域。第一极性类型的外部抽头围绕阱区域，并且桥接源区域和外部抽头。

7. 发明申请

US20100188787A1 METHOD AND APPARATUS TO REDUCE FOOTPRINT OF ESD PROTECTION WITHIN AN INTEGRATED CIRCUIT 有权
标题翻译：降低集成电路中ESD保护功能的方法和装置
公开(公告)号：US20100188787A1
公开(公告)日：2010-07-29
申请号：US12362471
申请日：2009-01-29
申请人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
发明人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
IPC分类号： H02H9/04 , H01L23/60
CPC分类号： H01L27/0266
摘要： An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.
摘要翻译：输入/输出（“I / O”）电路具有用硅化物块耦合到输入引脚的第一N沟道金属氧化物半导体（“NMOS”）场效应晶体管（“FET”）。第一P沟道金属氧化物半导体（“PMOS”）FET直接连接到输入引脚，其N阱电耦合到ESD阱偏置电路。 NMOS低压差分信号（“LVDS”）驱动器也直接连接到输入引脚，并具有级联的NMOS FET。 LVDS驱动器的第一个NMOS FET制造在电耦合到地的第一P抽头保护环和耦合到ESD阱偏置的N阱保护环上。 LVDS驱动器的第二个NMOS FET在与地耦合的第二个P分接保护环内制造。

8. 发明授权

US09058454B1 Method and apparatus to reduce power segmentation overhead within an integrated circuit 有权
标题翻译：降低集成电路内的功率分配开销的方法和装置
公开(公告)号：US09058454B1
公开(公告)日：2015-06-16
申请号：US12570637
申请日：2009-09-30
申请人： Steven P. Young , James Karp , Michael J. Hart
发明人： Steven P. Young , James Karp , Michael J. Hart
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F17/5045 , G06F17/505 , G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F2217/40 , G06F2217/78
摘要： A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.
摘要翻译：一种提供功率分配架构的方法和装置，其基本上消除了与常规功率分配架构相关联的路由和区域损失。功率开关部件配置在集成电路（IC）的外部互连部分内，以减少必须穿过的层间互连的数量，以便可编程地向IC的各种器件段提供工作功率。交替采用系统级封装（SIP）集成方法，由此在功率分配架构内使用的功率开关组件方便地分配在基极或堆叠管芯中，以减少层间互连的数量。功率开关组件也可以作为诸如晶体管或微型微型开关/继电器之类的离散开关组件而非芯片地实现。

9. 发明授权

US08519741B1 Operating a programmable integrated circuit with functionally equivalent configuration bitstreams 有权
标题翻译：操作具有功能等效配置比特流的可编程集成电路
公开(公告)号：US08519741B1
公开(公告)日：2013-08-27
申请号：US13543508
申请日：2012-07-06
申请人： James Karp , Michael J. Hart
发明人： James Karp , Michael J. Hart
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G06F17/5054 , H03K19/17736
摘要： Approaches for operating a programmable integrated circuit (IC) are disclosed. One configuration bitstream of two or more configuration bitstreams is selected. Each configuration bitstream implements a functionally equivalent circuit on the programmable IC and programs a respective subset of pass gates of the programmable IC. Each subset of pass gates programmed by the configuration bitstreams is disjoint from each other subset of pass gates. The programmable IC, which is defect-free, is configured with the selected configuration bitstream. The defect-free programmable IC is then operated for a period of time. The selecting, configuring and operating are repeated, and for successive selecting operations, different ones of the configuration bitstreams are selected.
摘要翻译：公开了用于操作可编程集成电路（IC）的方法。选择两个或多个配置比特流的一个配置比特流。每个配置比特流在可编程IC上实现功能上等效的电路，并对可编程IC的相应子集的通道进行编程。由配置比特流编程的每个通道的子集与传递门的每个其他子集不相交。无缺陷的可编程IC配置有所选配置比特流。然后，无缺陷的可编程IC运行一段时间。重复选择，配置和操作，并且对于连续选择操作，选择不同的配置比特流。

10. 发明授权

US08453092B2 T-coil network design for improved bandwidth and electrostatic discharge immunity 有权
标题翻译： T线圈网络设计，提高带宽和静电放电抗扰度
公开(公告)号：US08453092B2
公开(公告)日：2013-05-28
申请号：US13441809
申请日：2012-04-06
申请人： Vassili Kireev , James Karp , Toan D. Tran
发明人： Vassili Kireev , James Karp , Toan D. Tran
IPC分类号： G06F17/50 , H03K19/00 , H03K25/00 , H01F21/02 , H01F29/00 , H03K19/0175 , H03K19/003 , H01F27/28 , H01L25/07 , H01L25/16
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5077 , G06F17/5081 , G06F2217/82 , H01F21/02 , H01F27/28 , H01F29/00 , H01L25/071 , H01L25/16 , H01L2924/0002 , H03K19/00346 , H03K19/017509 , H03K19/017545 , H01L2924/00
摘要： An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.
摘要翻译：描述了一种电路的实施例，其包括第一电感器，其包括第一端和第二端，其中第一电感器的第一端形成电路的输入节点。电路的实施例还包括第二电感器，其包括第一端和第二端，其中第一电感器的第二端耦合到形成电路的输出节点的第二电感器的第一端; 耦合到所述第二电感器的第二端的电阻器; 以及静电放电结构，其耦合到所述输出节点并且被配置为提供一定量的静电放电保护，其中所述静电放电保护的量基于寄生桥电容和负载电容量度。

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