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1. 发明授权

US08134813B2 Method and apparatus to reduce footprint of ESD protection within an integrated circuit 有权
标题翻译：降低集成电路内ESD保护占地面积的方法和装置
公开(公告)号：US08134813B2
公开(公告)日：2012-03-13
申请号：US12362471
申请日：2009-01-29
申请人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
发明人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.
摘要翻译：输入/输出（“I / O”）电路具有用硅化物块耦合到输入引脚的第一N沟道金属氧化物半导体（“NMOS”）场效应晶体管（“FET”）。第一P沟道金属氧化物半导体（“PMOS”）FET直接连接到输入引脚，其N阱电耦合到ESD阱偏置电路。 NMOS低压差分信号（“LVDS”）驱动器也直接连接到输入引脚，并具有级联的NMOS FET。 LVDS驱动器的第一个NMOS FET制造在电耦合到地的第一P抽头保护环和耦合到ESD阱偏置的N阱保护环上。 LVDS驱动器的第二个NMOS FET在与地耦合的第二个P分接保护环内制造。

2. 发明申请

US20100188787A1 METHOD AND APPARATUS TO REDUCE FOOTPRINT OF ESD PROTECTION WITHIN AN INTEGRATED CIRCUIT 有权
标题翻译：降低集成电路中ESD保护功能的方法和装置
公开(公告)号：US20100188787A1
公开(公告)日：2010-07-29
申请号：US12362471
申请日：2009-01-29
申请人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
发明人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
IPC分类号： H02H9/04 , H01L23/60
CPC分类号： H01L27/0266
摘要： An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.
摘要翻译：输入/输出（“I / O”）电路具有用硅化物块耦合到输入引脚的第一N沟道金属氧化物半导体（“NMOS”）场效应晶体管（“FET”）。第一P沟道金属氧化物半导体（“PMOS”）FET直接连接到输入引脚，其N阱电耦合到ESD阱偏置电路。 NMOS低压差分信号（“LVDS”）驱动器也直接连接到输入引脚，并具有级联的NMOS FET。 LVDS驱动器的第一个NMOS FET制造在电耦合到地的第一P抽头保护环和耦合到ESD阱偏置的N阱保护环上。 LVDS驱动器的第二个NMOS FET在与地耦合的第二个P分接保护环内制造。

3. 发明授权

US08218277B2 Shared electrostatic discharge protection for integrated circuit output drivers 有权
标题翻译：用于集成电路输出驱动器的共享静电放电保护
公开(公告)号：US08218277B2
公开(公告)日：2012-07-10
申请号：US12555598
申请日：2009-09-08
申请人： Richard C. Li , James Karp
发明人： Richard C. Li , James Karp
IPC分类号： H02H9/00
CPC分类号： H01L27/0277
摘要： A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (Rsub) that initiates bipolar snapback in the MOSFET output driver at which an ESD event occurs. The value of Rsub depends upon a composite distance from the centroid of each MOSFET output driver to the contact ring.
摘要翻译：用于保护集成电路（IC）内的金属氧化物半导体场效应晶体管（MOSFET）输出驱动器从静电放电（ESD）的系统包括位于公共IC扩散材料内的第一MOSFET输出驱动器和第二MOSFET输出驱动器。该系统包括耦合到公共IC扩散材料并沿着围绕MOSFET输出驱动器的周边的外边缘布置的接触环。每个MOSFET输出驱动器的重心是周围围绕两个MOSFET输出驱动器的重心。每个MOSFET输出驱动器具有衬底电阻（Rsub）的值，该值引发ESD输出驱动器发生ESD事件时的双极性跳变。 Rsub的值取决于从每个MOSFET输出驱动器到接触环的质心的复合距离。

4. 发明申请

US20110058290A1 SHARED ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED CIRCUIT OUTPUT DRIVERS 有权
标题翻译：集成电路输出驱动器的共享静电放电保护
公开(公告)号：US20110058290A1
公开(公告)日：2011-03-10
申请号：US12555598
申请日：2009-09-08
申请人： Richard C. Li , James Karp
发明人： Richard C. Li , James Karp
IPC分类号： H02H9/00
CPC分类号： H01L27/0277
摘要： A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (Rsub) that initiates bipolar snapback in the MOSFET output driver at which an ESD event occurs. The value of Rsub depends upon a composite distance from the centroid of each MOSFET output driver to the contact ring.
摘要翻译：用于保护集成电路（IC）内的金属氧化物半导体场效应晶体管（MOSFET）输出驱动器从静电放电（ESD）的系统包括位于公共IC扩散材料内的第一MOSFET输出驱动器和第二MOSFET输出驱动器。该系统包括耦合到公共IC扩散材料并沿着围绕MOSFET输出驱动器的周边的外边缘布置的接触环。每个MOSFET输出驱动器的重心是周围围绕两个MOSFET输出驱动器的重心。每个MOSFET输出驱动器具有衬底电阻（Rsub）的值，该值引发ESD输出驱动器发生ESD事件时的双极性跳变。 Rsub的值取决于从每个MOSFET输出驱动器到接触环的质心的复合距离。

5. 发明授权

US6118324A Output driver with reduced ground bounce 失效
标题翻译：输出驱动器减少地面反弹
公开(公告)号：US6118324A
公开(公告)日：2000-09-12
申请号：US884822
申请日：1997-06-30
申请人： Richard C. Li , Hy V. Nguyen
发明人： Richard C. Li , Hy V. Nguyen
IPC分类号： H03K17/16
CPC分类号： H03K17/164
摘要： An output driver circuit including a first path from an output pad to ground through a first switch, and a second path from the output pad to ground through series-connected second and third switches. The first switch is directly connected to a pull-down signal source, and one of the second and third switches is connected to the pull-down signal source through a one-shot circuit. In a pull-up state, the first and second switches are opened, and the one-shot circuit generates a stabilized output signal which closes the third switch. When the output driver circuit switches to a pull-down state, the first switch is closed, thereby connecting the output pad to ground via the first path. The signal change also closes the second switch. In addition, due to a propagation delay of the second signal through the one-shot circuit, the third switch initially remains closed, thereby also connecting the output pad to ground via the second path. The one-shot circuit then opens the third switch before the output pad fully discharges. Subsequently, the one-shot circuit returns to its stabilized state and closes the third switch, thereby connecting the substantially fully discharged output pad to ground through both the first and second paths.
摘要翻译：一种输出驱动器电路，包括从第一开关从输出焊盘到接地的第一路径，以及通过串联连接的第二和第三开关从输出焊盘到接地的第二路径。第一开关直接连接到下拉信号源，第二和第三开关之一通过单触发电路连接到下拉信号源。在上拉状态下，第一和第二开关断开，单向电路产生稳定的输出信号，其闭合第三开关。当输出驱动器电路切换到下拉状态时，第一开关闭合，从而通过第一路径将输出焊盘连接到地。信号变化也关闭第二个开关。此外，由于通过单触发电路的第二信号的传播延迟，第三开关最初保持闭合，从而也通过第二路径将输出焊盘连接到地。然后，单触发电路在输出焊盘完全放电之前打开第三个开关。随后，单触发电路恢复到其稳定状态并关闭第三开关，从而通过第一和第二路径将基本完全放电的输出焊盘连接到地。

6. 发明授权

US5376843A TTL input buffer with on-chip reference bias regulator and decoupling capacitor 失效
标题翻译：具有片内基准偏置调节器和去耦电容的TTL输入缓冲器
公开(公告)号：US5376843A
公开(公告)日：1994-12-27
申请号：US929872
申请日：1992-08-11
申请人： Ta-Ke Tien , Chau-chin Wu , Richard C. Li
发明人： Ta-Ke Tien , Chau-chin Wu , Richard C. Li
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/20
CPC分类号： H03K19/00384 , H03K19/018521
摘要： An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.
摘要翻译：对电源电压，温度和其他操作参数变化不敏感的输入缓冲器包括去耦电容并接收参考电压。在一个实施例中，输入缓冲器包括CMOS反相器，其中提供PMOS晶体管以将输出信号与接地电压（“接地反弹”）的波动分离。在一个实施例中，带隙型电压调节器提供输入缓冲器的参考电压。

7. 发明授权

US5483183A Bipolar current sense amplifier 失效
标题翻译：双极电流检测放大器
公开(公告)号：US5483183A
公开(公告)日：1996-01-09
申请号：US194773
申请日：1994-02-10
申请人： Richard C. Li , Chau-Chin Wu , Ta-Ke Tien
发明人： Richard C. Li , Chau-Chin Wu , Ta-Ke Tien
IPC分类号： H03F3/45 , H03K5/24 , G01R19/00
CPC分类号： H03F3/45085 , H03K5/2418 , H03F2203/45352 , H03F2203/45374 , H03F2203/45544 , H03F2203/45564 , H03F2203/45654 , H03F2203/45702
摘要： In a sense amplifier, collectors of a first pair of transistors are connected to and drive the bases of a pair of output transistors, and the bases of the first pair of transistors and the emitters of the pair of output transistors are coupled to input nodes of the sense amplifier. The speed of the sense amplifier is enhanced over the prior art because changes in currents (or voltages) on the input nodes change both the emitter and base voltages of the pair of output transistors.
摘要翻译：在读出放大器中，第一对晶体管的集电极连接到一对输出晶体管的基极并驱动一对输出晶体管的基极，并且第一对晶体管的基极和一对输出晶体管的发射极耦合到读出放大器。由于输入节点上的电流（或电压）的变化改变了一对输出晶体管的发射极和基极电压，所以读出放大器的速度比现有技术增强。

8. 发明授权

US5477204A Radio frequency transformer 失效
标题翻译：射频变压器
公开(公告)号：US5477204A
公开(公告)日：1995-12-19
申请号：US270623
申请日：1994-07-05
申请人： Richard C. Li
发明人： Richard C. Li
IPC分类号： H01F17/00 , H01F19/08 , H03F1/56 , H04B1/48 , H01F27/28
CPC分类号： H01F17/0006 , H01F19/08 , H03F1/565 , H04B1/48 , H01F2017/0046
摘要： A transformer (100)includes a substrate (101) on which two substantially adjacent runners (124 and 126) are disposed. The two runners (124 and 126) have substantially the same width and the same length and run from one segment of the substrate to another forming two spirals. The spirals run in opposite directions thereby capturing the flux and preventing it from escaping from the substrate hence adding to the efficiency of the electromagnetic coupling. The insertion loss of the transformer (100) is minimized by the high dielectric constant of the substrate, the close proximity of the two runners (124 and 126), and the opposite direction of the two loops.
摘要翻译：变压器（100）包括其上设置有两个基本上相邻的流道（124和126）的基板（101）。两个流道（124和126）具有基本上相同的宽度和相同的长度并且从基底的一个区段到另一个区段形成两个螺旋。螺旋沿相反方向运行，从而捕获通量并防止其从基板逸出，从而增加了电磁耦合的效率。变压器（100）的插入损耗由于衬底的高介电常数，两个流道（124和126）的紧密接近以及两个回路的相反方向而被最小化。

9. 发明授权

US5933025A Low voltage interface circuit with a high voltage tolerance 失效
标题翻译：具有高电压容差的低压接口电路
公开(公告)号：US5933025A
公开(公告)日：1999-08-03
申请号：US784163
申请日：1997-01-15
申请人： Scott S. Nance , Mohammad R. Tamjidi , Richard C. Li , Jennifer Wong , Hassan K. Bazargan
发明人： Scott S. Nance , Mohammad R. Tamjidi , Richard C. Li , Jennifer Wong , Hassan K. Bazargan
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/09429 , H03K19/00315 , H03K19/018521
摘要： A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin. In high impedance mode when the externally applied voltage at the I/O pin is sufficiently below the interface circuit supply voltage, the isolation circuit is driven to approximately the interface circuit supply voltage. In low impedance mode the isolation circuitry is disabled and the logic level at the data terminal is transmitted to the I/O pin. One embodiment of the present invention provides a buffered data path from the data terminal to the I/O pin.
摘要翻译：具有高电压公差的低压接口电路使得具有不同电源电平的器件能够有效耦合在一起，而不会有明显的漏电流或电路损坏。本发明的一个实施例包括三态控制电路，数据通路，参考电压电路和隔离电路。接口电路提供高阻抗接收模式。在这种模式下，当接口电路的I / O引脚施加的电压足够大于接口电路电源电压时，隔离电路会将电源与I / O引脚隔离开来。接口电路还保护所有的晶体管从栅极到体积，栅极到源极和漏极到大于指定电压的电压降，例如对于额定3V电源的3.6V，当高达5.5V被外部施加到 I / O引脚。在高阻抗模式下，当I / O引脚的外部施加电压足够低于接口电路电源电压时，隔离电路被驱动到大致接口电路电源电压。在低阻模式下，隔离电路被禁用，数据端子的逻辑电平被传输到I / O引脚。本发明的一个实施例提供从数据终端到I / O引脚的缓冲数据路径。

10. 发明授权

US5898320A Programmable interconnect point having reduced crowbar current 失效
标题翻译：可编程互连点具有减少的撬棒电流
公开(公告)号：US5898320A
公开(公告)日：1999-04-27
申请号：US823270
申请日：1997-03-27
申请人： Richard C. Li , Hy V. Nguyen , Patrick J. Crotty
发明人： Richard C. Li , Hy V. Nguyen , Patrick J. Crotty
IPC分类号： H03K19/017
CPC分类号： H03K19/018585 , H03K19/00361
摘要： Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.
摘要翻译：通过在电源和地之间插入晶体管开关来解决由于缓冲的可编程互连点处的输入信号转换引起的与过量的短路电流相关的问题。插入的开关与输入缓冲器串联并由也控制互连的通过/不通过状态的存储器单元控制。断开插入开关在存储单元输出导致互连的无通状态时，阻断在切换期间流动的电流。

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