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1. 发明授权

US08134813B2 Method and apparatus to reduce footprint of ESD protection within an integrated circuit 有权
标题翻译：降低集成电路内ESD保护占地面积的方法和装置
公开(公告)号：US08134813B2
公开(公告)日：2012-03-13
申请号：US12362471
申请日：2009-01-29
申请人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
发明人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.
摘要翻译：输入/输出（“I / O”）电路具有用硅化物块耦合到输入引脚的第一N沟道金属氧化物半导体（“NMOS”）场效应晶体管（“FET”）。第一P沟道金属氧化物半导体（“PMOS”）FET直接连接到输入引脚，其N阱电耦合到ESD阱偏置电路。 NMOS低压差分信号（“LVDS”）驱动器也直接连接到输入引脚，并具有级联的NMOS FET。 LVDS驱动器的第一个NMOS FET制造在电耦合到地的第一P抽头保护环和耦合到ESD阱偏置的N阱保护环上。 LVDS驱动器的第二个NMOS FET在与地耦合的第二个P分接保护环内制造。

2. 发明申请

US20100188787A1 METHOD AND APPARATUS TO REDUCE FOOTPRINT OF ESD PROTECTION WITHIN AN INTEGRATED CIRCUIT 有权
标题翻译：降低集成电路中ESD保护功能的方法和装置
公开(公告)号：US20100188787A1
公开(公告)日：2010-07-29
申请号：US12362471
申请日：2009-01-29
申请人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
发明人： James Karp , Richard C. Li , Fu-Hing Ho , Mohammed Fakhruddin
IPC分类号： H02H9/04 , H01L23/60
CPC分类号： H01L27/0266
摘要： An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.
摘要翻译：输入/输出（“I / O”）电路具有用硅化物块耦合到输入引脚的第一N沟道金属氧化物半导体（“NMOS”）场效应晶体管（“FET”）。第一P沟道金属氧化物半导体（“PMOS”）FET直接连接到输入引脚，其N阱电耦合到ESD阱偏置电路。 NMOS低压差分信号（“LVDS”）驱动器也直接连接到输入引脚，并具有级联的NMOS FET。 LVDS驱动器的第一个NMOS FET制造在电耦合到地的第一P抽头保护环和耦合到ESD阱偏置的N阱保护环上。 LVDS驱动器的第二个NMOS FET在与地耦合的第二个P分接保护环内制造。

3. 发明授权

US06972939B1 Method and apparatus for a floating well RC triggered electrostatic discharge power clamp 有权
标题翻译：浮动井的方法和装置RC触发静电放电电源钳
公开(公告)号：US06972939B1
公开(公告)日：2005-12-06
申请号：US10871075
申请日：2004-06-18
申请人： Fu-Hing Ho , Patrick J. Crotty
发明人： Fu-Hing Ho , Patrick J. Crotty
IPC分类号： H01L27/02 , H02H3/22 , H02H9/00
CPC分类号： H01L27/0285 , H03K2217/0018
摘要： An Electrostatic Discharge (ESD) protection circuit activates an ESD conduction circuit in response to an ESD event. A deactivation circuit generates an exponentially increasing deactivation signal in response to the ESD event, such that once the deactivation signal has increased to a trigger point of a control circuit, the ESD conduction circuit is deactivated. An active resistance component within the deactivation circuit incorporates a biasing element to maintain a resistance value of the active resistance component substantially constant over all operating conditions.
摘要翻译：静电放电（ESD）保护电路响应ESD事件激活ESD导通电路。停用电路响应于ESD事件而产生指数增加的去激活信号，使得一旦去激活信号已经增加到控制电路的触发点，则ESD导通电路被去激活。去激活电路内的有源电阻分量包含偏置元件，以在所有操作条件下保持有源电阻分量的电阻值基本上恒定。

4. 发明授权

US07372679B1 Method and apparatus for RC triggered electrostatic discharge power clamp with hysteresis 有权
标题翻译：具有迟滞功能的RC触发静电放电电源钳的方法和装置
公开(公告)号：US07372679B1
公开(公告)日：2008-05-13
申请号：US10871070
申请日：2004-06-18
申请人： Fu-Hing Ho , Patrick J. Crotty , Andy T. Nguyen
发明人： Fu-Hing Ho , Patrick J. Crotty , Andy T. Nguyen
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H01L27/0285
摘要： An Electrostatic Discharge (ESD) protection device extends the protection range of an ESD clamp circuit through hysteresis of the associated ESD clamp control circuit. Once the ESD clamp circuit is activated, an adjustment circuit applies a trigger level adjustment signal to the ESD clamp control circuit. The trigger level adjustment signal effectively increases the magnitude of the deactivation signal that is required to deactivate the ESD clamp circuit. Since the deactivation signal increases over time, a longer activation time of the ESD protection device is provided, which allows an extended protection range.
摘要翻译：静电放电（ESD）保护装置通过相关ESD钳位控制电路的滞后来延长ESD钳位电路的保护范围。一旦ESD钳位电路被激活，调整电路就向ESD钳位控制电路施加触发电平调整信号。触发电平调整信号有效地增加去激活ESD钳位电路所需的去激活信号的幅度。由于去激活信号随着时间的推移而增加，所以提供了ESD保护装置的较长的激活时间，这允许扩展的保护范围。

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