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1. 发明授权

US09058454B1 Method and apparatus to reduce power segmentation overhead within an integrated circuit 有权
标题翻译：降低集成电路内的功率分配开销的方法和装置
公开(公告)号：US09058454B1
公开(公告)日：2015-06-16
申请号：US12570637
申请日：2009-09-30
申请人： Steven P. Young , James Karp , Michael J. Hart
发明人： Steven P. Young , James Karp , Michael J. Hart
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F17/5045 , G06F17/505 , G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F2217/40 , G06F2217/78
摘要： A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.
摘要翻译：一种提供功率分配架构的方法和装置，其基本上消除了与常规功率分配架构相关联的路由和区域损失。功率开关部件配置在集成电路（IC）的外部互连部分内，以减少必须穿过的层间互连的数量，以便可编程地向IC的各种器件段提供工作功率。交替采用系统级封装（SIP）集成方法，由此在功率分配架构内使用的功率开关组件方便地分配在基极或堆叠管芯中，以减少层间互连的数量。功率开关组件也可以作为诸如晶体管或微型微型开关/继电器之类的离散开关组件而非芯片地实现。

2. 发明授权

US07452765B1 Single event upset in SRAM cells in FPGAs with high resistivity gate structures 有权
标题翻译：在具有高电阻率栅极结构的FPGA中的SRAM单元中的单事件不正常
公开(公告)号：US07452765B1
公开(公告)日：2008-11-18
申请号：US11242409
申请日：2005-09-30
申请人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
发明人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
IPC分类号： H01L21/8238
CPC分类号： H01L27/11803 , H01L21/76831 , H01L21/76834 , H01L27/11
摘要： SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
摘要翻译： SEU硬化串联电阻负载形成在锁存器的交叉耦合反相器的栅极结构内。对于一些实施例，用于每个交叉耦合的反相器的输入的栅极接触具有足够高的电阻以提供SEU-硬化串联电阻。对于其他实施例，耦合到每个交叉耦合的反相器的输入的导电迹线层包括提供SEU硬化串联电阻的高电阻部分。

3. 发明授权

US06982451B1 Single event upset in SRAM cells in FPGAs with high resistivity gate structures 有权
标题翻译：在具有高电阻率栅极结构的FPGA中的SRAM单元中的单事件不正常
公开(公告)号：US06982451B1
公开(公告)日：2006-01-03
申请号：US10402446
申请日：2003-03-27
申请人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
发明人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
IPC分类号： H01L27/108
CPC分类号： H01L27/11803 , H01L21/76831 , H01L21/76834 , H01L27/11
摘要： SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
摘要翻译： SEU硬化串联电阻负载形成在锁存器的交叉耦合反相器的栅极结构内。对于一些实施例，用于每个交叉耦合的反相器的输入的栅极接触具有足够高的电阻以提供SEU-硬化串联电阻。对于其他实施例，耦合到每个交叉耦合的反相器的输入的导电迹线层包括提供SEU硬化串联电阻的高电阻部分。

4. 发明授权

US06777978B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
公开(公告)号：US06777978B2
公开(公告)日：2004-08-17
申请号：US10624617
申请日：2003-07-21
申请人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
IPC分类号： H03K19173
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

5. 发明授权

US07089527B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
公开(公告)号：US07089527B2
公开(公告)日：2006-08-08
申请号：US10853982
申请日：2004-05-25
申请人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
IPC分类号： G06F17/50
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

6. 发明授权

US06768335B1 Integrated circuit multiplexer including transistors of more than one oxide thickness 有权
标题翻译：集成电路多路复用器包括多于一个氧化物厚度的晶体管
公开(公告)号：US06768335B1
公开(公告)日：2004-07-27
申请号：US10354520
申请日：2003-01-30
申请人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F738
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译：可以用于例如可编程逻辑器件（PLD）中的多路复用器。多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

7. 发明申请

US20090121737A1 CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY 失效
标题翻译：通过分离设备来表征电路性能和对信号延迟的互连影响
公开(公告)号：US20090121737A1
公开(公告)日：2009-05-14
申请号：US12355988
申请日：2009-01-19
申请人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
发明人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
IPC分类号： G01R31/26 , G01R31/02 , H01L23/58
CPC分类号： G01R31/2882 , G01R31/318511 , G01R31/318516 , G01R31/3187
摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
摘要翻译：集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

8. 发明授权

US07724016B2 Characterizing circuit performance by separating device and interconnect impact on signal delay 失效
标题翻译：通过分离器件和互连对信号延迟的影响来表征电路性能
公开(公告)号：US07724016B2
公开(公告)日：2010-05-25
申请号：US12355988
申请日：2009-01-19
申请人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
发明人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
IPC分类号： G01R31/02
CPC分类号： G01R31/2882 , G01R31/318511 , G01R31/318516 , G01R31/3187
摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
摘要翻译：集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

9. 发明授权

US06949951B1 Integrated circuit multiplexer including transistors of more than one oxide thickness 有权
标题翻译：集成电路多路复用器包括多于一个氧化物厚度的晶体管
公开(公告)号：US06949951B1
公开(公告)日：2005-09-27
申请号：US10869777
申请日：2004-06-15
申请人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F7/38 , H03K17/00 , H03K17/693 , H03K19/177
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译：可以用于例如可编程逻辑器件（PLD）中的多路复用器。多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

10. 发明授权

US06621325B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
标题翻译：用于选择性地将井偏压施加到可编程设备的部分的结构和方法
公开(公告)号：US06621325B2
公开(公告)日：2003-09-16
申请号：US09956203
申请日：2001-09-18
申请人： Michael J. Hart , Steven P. Young , Daniel Gitlin , Hua Shen , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Daniel Gitlin , Hua Shen , Stephen M. Trimberger
IPC分类号： H03K301
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.
摘要翻译：用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。在一个实施例中，FPGA实现软件自动地确定关键路径并且生成配置比特流，其使得能够仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行偏置。在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。

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