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1. 发明授权

US07199834B2 Vertical synchronizing signal generation apparatus and video signal processing apparatus 有权
标题翻译：垂直同步信号发生装置和视频信号处理装置
公开(公告)号：US07199834B2
公开(公告)日：2007-04-03
申请号：US10480235
申请日：2002-06-07
申请人： Kunihiko Fujii , Toshihiro Miyoshi , Kazuhide Fujimoto , Manabu Yumine , Toshiya Noritake
发明人： Kunihiko Fujii , Toshihiro Miyoshi , Kazuhide Fujimoto , Manabu Yumine , Toshiya Noritake
IPC分类号： H04N5/06 , H04N5/95
CPC分类号： H04N5/12 , H04N5/10
摘要： The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.
摘要翻译：垂直同步信号发生器包括：垂直同步信号分离电路，用于分离输入亮度信号的垂直同步信号并输出分离信号作为第一垂直同步信号; 自动频率控制电路，用于产生具有与第一垂直同步信号的平均重复频率对应的重复频率的第二垂直同步信号，并输出所产生的信号; 垂直同步信号相位检测电路，用于检测第一垂直同步信号是否具有交替重复的两个不同周期，并将检测结果作为判定信号输出; 以及选择器，用于接收第一和第二垂直同步信号，当判定信号指示第一垂直同步信号具有交替重复的两个不同周期时，选择第一垂直同步信号，否则选择第二垂直同步信号并输出所选择的信号。

2. 发明授权

US06724430B2 Sampling frequency converter, sampling frequency conversion method, video signal processor, and video signal processing method 失效
标题翻译：采样变频器，采样频率转换方法，视频信号处理器和视频信号处理方法
公开(公告)号：US06724430B2
公开(公告)日：2004-04-20
申请号：US09820312
申请日：2001-03-29
申请人： Toshihiro Miyoshi , Hisaji Murata , Manabu Yumine
发明人： Toshihiro Miyoshi , Hisaji Murata , Manabu Yumine
IPC分类号： H04N701
CPC分类号： H04N9/89 , H04N9/64
摘要： A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.
摘要翻译：一个DD转换器电路109，用于内插锁定到14.3MHz突发时钟的数字视频信号以将采样数据转换成13.5-NHz的自由运行时钟;以及帧存储器电路110，用于写入包括由DD转换器电路109在14.3MHz突发时钟上输出的数字视频信号以及在13.5MHz时钟S112上读取写入的数字视频信号。因此，可以提供可以在不使用模拟PLL电路的情况下实现数字视频信号的速率转换的视频信号处理器。

3. 发明申请

US20080211962A1 FRAME SYNCHRONIZER CIRCUIT 审中-公开
标题翻译：帧同步电路
公开(公告)号：US20080211962A1
公开(公告)日：2008-09-04
申请号：US11960108
申请日：2007-12-19
申请人： Hisaji Murata , Toshihiro Miyoshi , Nariaki Yamamoto
发明人： Hisaji Murata , Toshihiro Miyoshi , Nariaki Yamamoto
IPC分类号： H04N5/04
CPC分类号： H04N7/0105 , H04N5/04 , H04N5/10
摘要： When it is detected that a write address signal and a read address signal coincide with each other during in the judgment range state, an address value of the write address signal is held to halt writing into a memory, whereby a video signal is outputted without mixing old and new frames therein. Therefore, a buffer area in the memory can be minimized, and an address control circuit can be appropriately controlled even when the frame frequency difference exceed a buffer capacity, thereby a frame synchronizer circuit that can output normal pictures is provided.
摘要翻译：当在判断范围状态期间检测到写入地址信号和读取地址信号彼此一致时，写入地址信号的地址值被保持以停止写入存储器，从而在不混合的情况下输出视频信号旧帧和新帧。因此，即使帧频差超过缓冲器容量，也可以使存储器中的缓冲区域最小化，并且可以适当地控制地址控制电路，从而提供能够输出正常图像的帧同步器电路。

4. 发明授权

US06483550B1 Video signal level converting device and video signal analog-to-digital converter 失效
标题翻译：视频信号电平转换器和视频信号模数转换器
公开(公告)号：US06483550B1
公开(公告)日：2002-11-19
申请号：US09320462
申请日：1999-05-27
申请人： Hisaji Murata , Toshihiro Miyoshi
发明人： Hisaji Murata , Toshihiro Miyoshi
IPC分类号： H04N514
CPC分类号： H04N9/64 , H04N5/20 , H04N11/20
摘要： An analog-to-digital converter for converting an analog television signal to a signal in compliance with a digital encoding standard is provided. The analog-to-digital converter according to the invention comprises an A-D converter circuit for converting an analog television signal to a 2n-bit digital signal, a synchronizing signal detecting circuit for detecting a synchronizing signal from the digital signal received from the A-D converter circuit, a Y/C separating circuit for separating a luminance signal and a carrier chrominance signal from the digital signal from the A-D converter circuit using the synchronizing signal from the synchronizing signal detecting circuit, a synchronizing signal converter circuit for converting a synchronizing signal portion of the luminance signal into a predetermined value, and a digital amplifying circuit for digitally amplifying the signal level from the synchronizing signal converter by a predetermined multiple value specified by a standard for communication or for video signal apparatus. The digital amplifying circuit may be composed of a shifter. A low pass filter may be used additionally to eliminate rounding errors. Further, depending on the type of video signal, the low pass filter may be bypassed.
摘要翻译：提供了一种用于将模拟电视信号转换为符合数字编码标准的信号的模拟 - 数字转换器。根据本发明的模数转换器包括用于将模拟电视信号转换为2n位数字信号的AD转换器电路，用于从AD转换器电路接收的数字信号中检测同步信号的同步信号检测电路，用于使用来自同步信号检测电路的同步信号从AD转换器电路的数字信号分离亮度信号和载波色度信号的Y / C分离电路，用于转换来自同步信号检测电路的同步信号部分的同步信号转换器电路亮度信号变为预定值，以及数字放大电路，用于将来自同步信号转换器的信号电平数字放大由通信标准或视频信号装置指定的预定多值。数字放大电路可以由移位器组成。另外可以使用低通滤波器来消除舍入误差。此外，根据视频信号的类型，可以旁路低通滤波器。

5. 发明授权

US6137537A Television receiver for receiving multi-standards 失效
标题翻译：用于接收多标准的电视接收机
公开(公告)号：US6137537A
公开(公告)日：2000-10-24
申请号：US162398
申请日：1998-09-28
申请人： Toshiaki Tsuji , Naoki Kurita , Minoru Miyata , Toshihiro Miyoshi
发明人： Toshiaki Tsuji , Naoki Kurita , Minoru Miyata , Toshihiro Miyoshi
IPC分类号： H04N5/46 , H04N5/44 , H04N5/445 , H04N5/45
CPC分类号： H04N5/46
摘要： A multi-standard television receiver in accordance with the present invention includes a plurality of video signal processing blocks having tristate functions at their output terminals, at least one memory block used in common for a plurality of video signal processing blocks and a video signal processing selection means for selecting one of the video signal processing blocks and independently controlling the output terminals of the video signal processing blocks using elements having a tristate function and can reduce power consumption by working only a selected video signal processing block and stopping the other video signal processing blocks. Further, using elements having a tristate function, possibility of element breakdown at selection and control of the elements can be removed.
摘要翻译：根据本发明的多标准电视接收机包括在其输出端子具有三态功能的多个视频信号处理块，用于多个视频信号处理块的共同使用的至少一个存储块和视频信号处理选择用于选择一个视频信号处理块的装置，并且使用具有三态功能的元件独立地控制视频信号处理块的输出端，并且可以通过仅操作所选择的视频信号处理块并停止其它视频信号处理块来降低功耗。此外，使用具有三态功能的元件，可以去除元件的选择和控制时的元件击穿的可能性。

6. 发明授权

US5163053A Audio signal demodulation circuit 失效
标题翻译：音频信号解调电路
公开(公告)号：US5163053A
公开(公告)日：1992-11-10
申请号：US499349
申请日：1990-08-06
申请人： Naoji Okumura , Toshihiro Miyoshi , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
发明人： Naoji Okumura , Toshihiro Miyoshi , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
IPC分类号： H04N5/60 , H04B1/10 , H04B14/04 , H04N7/088
CPC分类号： H04N7/088 , H04B14/046
摘要： An audio signal demodulating circuit comprises a counter circuit (11) for detecting the number of samples for which interpolation is to be successively made by counting the output from an error correction circuit (2) and an AND circuit 10 for taking the logical product of the output from the counter circuit and the mute signal generated when synchronization has been lost. If interpolation is to be successively made for m (integer) or more, an audio differential signal is muted using a mute signal so as to remove the signal with greatly deteriorated audio quality. This can remove large audio distortion generated if interpolation is only successively made for error correction when errors successively occur for samples.
摘要翻译： PCT No.PCT / JP89 / 01088 Sec。 371日期1990年8月6日 102（e）日期1990年8月6日PCT提交1989年10月14日PCT公布。出版物WO90 / 04890 日期：1990年5月3日。音频信号解调电路包括计数器电路（11），用于通过对来自纠错电路（2）的输出和AND电路10进行计数来检测要连续进行内插的采样数，取计数器电路输出的逻辑积和同步丢失时产生的静音信号。如果要连续进行m（整数）以上的插补，则使用静音信号使音频差分信号静音，以便消除音频质量大大恶化的信号。这可以消除当针对样本连续发生错误时仅针对纠错连续进行插值时产生的大音频失真。

7. 发明授权

US5153724A Video signal switching circuit especially suitable for high definition television receiving 失效
标题翻译：视频信号切换电路特别适用于高分辨率电视接收
公开(公告)号：US5153724A
公开(公告)日：1992-10-06
申请号：US499351
申请日：1990-08-06
申请人： Toshihiro Miyoshi , Hideyuki Ikuhara , Yuichi Ninomiya , Toshiro Ohmura
发明人： Toshihiro Miyoshi , Hideyuki Ikuhara , Yuichi Ninomiya , Toshiro Ohmura
IPC分类号： H04N5/04 , H04N7/015
CPC分类号： H04N7/015 , H04N5/44
摘要： The present invention provides an apparatus which receives and displays a high definition television signal and which is constructed so that noise and/or a deformed picture may not be displayed even when an input signal instead of a high definition television signal is applied or when transmission of such a high definition television signal is interrupted. In the apparatus, on the basis of whether or not a frame signal in an input high definition television signal can be detected, a first signal indicating synchronization lock or a second signal indicating synchronization unlock is generated so that, when the first signal is detected, the output of a signal processing circuit (110) is selected to display the high definition television signal, while when the second signal is detected, the output of a pattern generation circuit (114) is selected to prevent display of noise etc.
摘要翻译： PCT No.PCT / JP88 / 01085 Sec。 371日期1990年8月6日 102（e）日期1990年8月6日PCT提交1989年10月24日PCT公布。出版物WO90 / 04904 1990年3月5日。本发明提供了一种接收和显示高分辨率电视信号的装置，其被构造成使得即使当输入信号代替高分辨率电视时也可能不显示噪声和/或变形图像信号被施加或当这种高清晰度电视信号的传输被中断时。在该装置中，基于是否能够检测输入高清晰度电视信号中的帧信号，产生表示同步锁定的第一信号或表示同步解锁的第二信号，使得当检测到第一信号时，选择信号处理电路（110）的输出以显示高分辨率电视信号，而当检测到第二信号时，选择图案产生电路（114）的输出以防止噪声的显示等。

8. 发明授权

US4984081A Apparatus for receiving and selecting high-definition television (HDTV) signals and standard television (NTSC) signals 失效
标题翻译：用于接收和选择高分辨率电视（HDTV）信号和标准电视（NTSC）信号的装置
公开(公告)号：US4984081A
公开(公告)日：1991-01-08
申请号：US301034
申请日：1989-01-24
申请人： Toshihiro Miyoshi , Masahiro Kawashima , Hideyuki Ikuhara , Tetsuo Kutsuki , Kazuyasu Yamamoto
发明人： Toshihiro Miyoshi , Masahiro Kawashima , Hideyuki Ikuhara , Tetsuo Kutsuki , Kazuyasu Yamamoto
IPC分类号： H04N5/44
CPC分类号： H04N7/0122
摘要： An apparatus for receiving and selecting high-definition television signals and NTSC standard television signals includes a high-definition display screen device having an aspect ratio of 16 to 9. The NTSC standard television signals have an aspect ratio which is different than the 16 to 9 aspect ratio of the high-definition display screen device. A first signal converter is for converting the NTSC standard television signals into first quasi-high-definition television signals identifying a first displayed image corresponding in vertical length to a vertical length of the high-definition display screen device. A second signal converter is for converting the NTSC standard television signals into second quasi-high-definition television signals identifying a second displayed image corresponding in horizontal length to a horizontal length of the high-definition display screen device. Switching circuits are provided for selecting one of the high-definition television signals and the first and second quasi-high-definition television signals.
摘要翻译：一种用于接收和选择高分辨率电视信号和NTSC标准电视信号的装置包括具有16至9的宽高比的高分辨率显示屏幕设备.NTSC标准电视信号的宽高比不同于16到9 高清显示屏设备的宽高比。第一信号转换器用于将NTSC标准电视信号转换为第一准高清晰度电视信号，其将垂直长度对应的第一显示图像识别为高清晰度显示屏设备的垂直长度。第二信号转换器用于将NTSC标准电视信号转换成识别与水平长度对应的第二显示图像与高分辨率显示屏设备的水平长度的第二准高清晰度电视信号。提供开关电路用于选择高分辨率电视信号和第一和第二准高清晰度电视信号之一。

9. 发明授权

US5363384A Audio signal demodulation circuit 失效
标题翻译：音频信号解调电路
公开(公告)号：US5363384A
公开(公告)日：1994-11-08
申请号：US164996
申请日：1993-12-10
申请人： Toshihiro Miyoshi , Naoji Okumura , Hisashi Arita , Kenji Ishikawa , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
发明人： Toshihiro Miyoshi , Naoji Okumura , Hisashi Arita , Kenji Ishikawa , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
IPC分类号： H04B14/04 , H04N7/088 , H04N5/76 , G06F11/00
CPC分类号： H04B14/046 , H04N7/088
摘要： A digital audio signal demodulation circuit comprises a synchronous detection circuit (18) and a muting circuit (17) for muting the output from an interpolation circuit (16) using a synchronization lock signal generated from the synchronous detection circuit (18) when synchronization has been lost. The differential signal output from the interpolation circuit (16) is muted by the muting circuit (17) and thereafter integrated by an integration circuit (19). Thus, an audio signal with high sound quality can be demodulated without producing interruption noise even when synchronization has been lost or forcible muting is done.
摘要翻译：数字音频信号解调电路包括同步检测电路（18）和静噪电路（17），用于在同步已经被同步时使用从同步检测电路（18）产生的同步锁定信号来使内插电路（16）的输出静音丢失。由内插电路（16）输出的差分信号由静噪电路（17）静音，然后由积分电路（19）进行积分。因此，即使在同步失去或强制静音完成的情况下，也能够解调高音质的音频信号而不产生中断噪声。

10. 发明授权

US5097333A Interframe deinterleave switching circuit 失效
标题翻译： INTERFRAME灭火器切换电路
公开(公告)号：US5097333A
公开(公告)日：1992-03-17
申请号：US499350
申请日：1990-08-06
申请人： Naoji Okumura , Toshihiro Miyoshi , Yuichi Ninomiya , Toshiro Ohmura
发明人： Naoji Okumura , Toshihiro Miyoshi , Yuichi Ninomiya , Toshiro Ohmura
IPC分类号： H03M13/27 , H04N5/04 , H04N7/015 , H04N7/62
CPC分类号： H04N21/4302 , H03M13/2789 , H04N21/8106 , H04N7/0152
摘要： In processing the transfer of digital voice signals, an interframe deinterleave switching circuit automatically switches the interleaving length without requiring any switching signal from the external unit. The circuit detects a voice synchronizing signal, produces a switching signal when the voice synchronizing signal is not detected, and inputs the switching signal to an interframe deinterleaving circuit (I) so that the interleaving length is automatically switched in synchronism therewith.
摘要翻译： PCT No.PCT / JP89 / 01086 Sec。 371日期1990年8月6日 102（e）日期1990年8月6日PCT提交1989年10月24日PCT公布。出版物WO90 / 04905 日期为1990年5月3日。在处理数字语音信号的传送中，帧间去交织切换电路自动切换交织长度，而不需要来自外部单元的任何切换信号。该电路检测语音同步信号，当没有检测到语音同步信号时产生切换信号，并将切换信号输入到帧间解交织电路（I），使得交织长度与其自动切换。

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