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1. 发明授权

US5363384A Audio signal demodulation circuit 失效
标题翻译：音频信号解调电路
公开(公告)号：US5363384A
公开(公告)日：1994-11-08
申请号：US164996
申请日：1993-12-10
申请人： Toshihiro Miyoshi , Naoji Okumura , Hisashi Arita , Kenji Ishikawa , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
发明人： Toshihiro Miyoshi , Naoji Okumura , Hisashi Arita , Kenji Ishikawa , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
IPC分类号： H04B14/04 , H04N7/088 , H04N5/76 , G06F11/00
CPC分类号： H04B14/046 , H04N7/088
摘要： A digital audio signal demodulation circuit comprises a synchronous detection circuit (18) and a muting circuit (17) for muting the output from an interpolation circuit (16) using a synchronization lock signal generated from the synchronous detection circuit (18) when synchronization has been lost. The differential signal output from the interpolation circuit (16) is muted by the muting circuit (17) and thereafter integrated by an integration circuit (19). Thus, an audio signal with high sound quality can be demodulated without producing interruption noise even when synchronization has been lost or forcible muting is done.
摘要翻译：数字音频信号解调电路包括同步检测电路（18）和静噪电路（17），用于在同步已经被同步时使用从同步检测电路（18）产生的同步锁定信号来使内插电路（16）的输出静音丢失。由内插电路（16）输出的差分信号由静噪电路（17）静音，然后由积分电路（19）进行积分。因此，即使在同步失去或强制静音完成的情况下，也能够解调高音质的音频信号而不产生中断噪声。

2. 发明授权

US5121212A Audio signal demodulating circuit with reduced power consumption 失效
标题翻译：具有降低功耗的音频信号解调电路
公开(公告)号：US5121212A
公开(公告)日：1992-06-09
申请号：US499353
申请日：1990-08-06
申请人： Naoji Okumura , Hisashi Arita , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
发明人： Naoji Okumura , Hisashi Arita , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
IPC分类号： H04B1/16 , H04N5/60 , H04N7/015 , H04N7/088
CPC分类号： H04N5/602 , H04N7/015 , H04N7/088
摘要： In an audio signal demodulating circuit, an externally supplied reference clock signal is frequency-divided so that the frequency-divided clock signals are supplied to circuit units constituting the audio signal demodulating circuit as clock signals having lower frequencies. A logic circuit is provided to respond to a timing pulse generated synchronously with a video signal so as to set input data or clock signals supplied to the aforementioned circuit units to a low level or a high level during a time period other than the time period of an audio signal, whereby electric power consumption in the audio signal demodulating circuit is markedly reduced.
摘要翻译： PCT No.PCT / JP89 / 01087 Sec。 371日期1990年8月6日 102（e）日期1990年8月6日PCT提交1989年10月24日PCT公布。出版物WO90 / 04901 日期为1990年5月3日。在音频信号解调电路中，外部提供的参考时钟信号被分频，使得分频时钟信号被提供给构成音频信号解调电路的电路单元作为具有较低频率的时钟信号。提供逻辑电路以对与视频信号同步产生的定时脉冲进行响应，以将提供给前述电路单元的输入数据或时钟信号设置为低电平或高电平，而不是在时间段音频信号，由此音频信号解调电路中的功耗明显降低。

3. 发明授权

US5163053A Audio signal demodulation circuit 失效
标题翻译：音频信号解调电路
公开(公告)号：US5163053A
公开(公告)日：1992-11-10
申请号：US499349
申请日：1990-08-06
申请人： Naoji Okumura , Toshihiro Miyoshi , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
发明人： Naoji Okumura , Toshihiro Miyoshi , Yuichi Ninomiya , Yoshimichi Ohtsuka , Tadashi Kawashima , Takushi Iwamoto
IPC分类号： H04N5/60 , H04B1/10 , H04B14/04 , H04N7/088
CPC分类号： H04N7/088 , H04B14/046
摘要： An audio signal demodulating circuit comprises a counter circuit (11) for detecting the number of samples for which interpolation is to be successively made by counting the output from an error correction circuit (2) and an AND circuit 10 for taking the logical product of the output from the counter circuit and the mute signal generated when synchronization has been lost. If interpolation is to be successively made for m (integer) or more, an audio differential signal is muted using a mute signal so as to remove the signal with greatly deteriorated audio quality. This can remove large audio distortion generated if interpolation is only successively made for error correction when errors successively occur for samples.
摘要翻译： PCT No.PCT / JP89 / 01088 Sec。 371日期1990年8月6日 102（e）日期1990年8月6日PCT提交1989年10月14日PCT公布。出版物WO90 / 04890 日期：1990年5月3日。音频信号解调电路包括计数器电路（11），用于通过对来自纠错电路（2）的输出和AND电路10进行计数来检测要连续进行内插的采样数，取计数器电路输出的逻辑积和同步丢失时产生的静音信号。如果要连续进行m（整数）以上的插补，则使用静音信号使音频差分信号静音，以便消除音频质量大大恶化的信号。这可以消除当针对样本连续发生错误时仅针对纠错连续进行插值时产生的大音频失真。

4. 发明授权

US5097333A Interframe deinterleave switching circuit 失效
标题翻译： INTERFRAME灭火器切换电路
公开(公告)号：US5097333A
公开(公告)日：1992-03-17
申请号：US499350
申请日：1990-08-06
申请人： Naoji Okumura , Toshihiro Miyoshi , Yuichi Ninomiya , Toshiro Ohmura
发明人： Naoji Okumura , Toshihiro Miyoshi , Yuichi Ninomiya , Toshiro Ohmura
IPC分类号： H03M13/27 , H04N5/04 , H04N7/015 , H04N7/62
CPC分类号： H04N21/4302 , H03M13/2789 , H04N21/8106 , H04N7/0152
摘要： In processing the transfer of digital voice signals, an interframe deinterleave switching circuit automatically switches the interleaving length without requiring any switching signal from the external unit. The circuit detects a voice synchronizing signal, produces a switching signal when the voice synchronizing signal is not detected, and inputs the switching signal to an interframe deinterleaving circuit (I) so that the interleaving length is automatically switched in synchronism therewith.
摘要翻译： PCT No.PCT / JP89 / 01086 Sec。 371日期1990年8月6日 102（e）日期1990年8月6日PCT提交1989年10月24日PCT公布。出版物WO90 / 04905 日期为1990年5月3日。在处理数字语音信号的传送中，帧间去交织切换电路自动切换交织长度，而不需要来自外部单元的任何切换信号。该电路检测语音同步信号，当没有检测到语音同步信号时产生切换信号，并将切换信号输入到帧间解交织电路（I），使得交织长度与其自动切换。

5. 发明授权

US5831684A Subpicture image signal vertical compression circuit 失效
标题翻译：子画面图像信号垂直压缩电路
公开(公告)号：US5831684A
公开(公告)日：1998-11-03
申请号：US657643
申请日：1996-05-30
申请人： Tomoko Morita , Naoji Okumura , Masahiro Tani
发明人： Tomoko Morita , Naoji Okumura , Masahiro Tani
IPC分类号： H04N5/45
CPC分类号： H04N5/45
摘要： A subpicture image signal vertical compression circuit for vertically compressing subpictures operating at respective synchronous timings different from that of the main picture when a plurality of image signals having respectively different synchronizations are displayed on an image display device. Depending on whether the field polarities of main and sub pictures are the same or not, the subpicture image signal vertical compression circuit generates suitable offsets for the first and the second fields to adjust the phases and prevent the inversion of the scan order in the vertical direction, at the first field and the second field of subpicture signal, after the phase adjustment to obtain a subpicture image with natural motion in the vertical direction.
摘要翻译：一种副图像图像信号垂直压缩电路，用于当在图像显示装置上显示具有不同同步的多个图像信号时，垂直压缩在与主图像不同的同步定时工作的子图像。根据主图像和副图像的场极性是否相同，子画面图像信号垂直压缩电路产生用于第一和第二场的适当偏移量以调整相位并防止垂直方向上的扫描顺序的反转在第一场和第二场子画面信号之后，进行相位调整，以在垂直方向上获得具有自然运动的子画面图像。

6. 发明授权

US5686970A Average luminance level detection apparatus and aspect ratio auto-discrimination apparatus for a television signal using the same 失效
标题翻译：平均亮度等级检测装置和使用其的电视信号的宽高比自动判别装置
公开(公告)号：US5686970A
公开(公告)日：1997-11-11
申请号：US569278
申请日：1995-12-08
申请人： Masahiro Tani , Naoji Okumura
发明人： Masahiro Tani , Naoji Okumura
IPC分类号： H04N5/44 , H04N5/46
CPC分类号： H04N7/0122 , Y10S348/913
摘要： A high precision aspect ratio auto-discrimination apparatus used for display apparatuses and television receivers comprising: an apparatus for detecting the upper edge and lower edge of a letter box picture through detecting the average luminance of every horizontal scan period; an apparatus for detecting respective average luminance levels in a plurality of specific regions in one field picture controlled by a horizontal synchronous signal and a vertical synchronous signal; and, an aspect ratio discrimination section to which the outputs of said both apparatuses are input.
摘要翻译：一种用于显示装置和电视接收机的高精度纵横比自动识别装置，包括：检测每个水平扫描周期的平均亮度的用于检测信箱图像的上边缘和下边缘的装置; 用于检测由水平同步信号和垂直同步信号控制的一个场图像中的多个特定区域中的各个平均亮度水平的装置; 以及输入所述两个装置的输出的宽高比判别部。

7. 发明授权

US5270815A Image compression processing apparatus having means for removing jitter contained at boundary between image and mask portions 失效
标题翻译：图像压缩处理设备具有用于去除包含在图像和掩模部分之间边界处的抖动的装置
公开(公告)号：US5270815A
公开(公告)日：1993-12-14
申请号：US791225
申请日：1991-11-13
申请人： Naoji Okumura , Hirohiko Sakashita
发明人： Naoji Okumura , Hirohiko Sakashita
IPC分类号： H04N5/262 , H04N7/01
CPC分类号： H04N7/0122
摘要： Input analog image signals are converted to digital image signals and applied to a demodulation circuit and a synchronous circuit. In the demodulation circuit, the digital image signals are demodulated and then compressed by a compression circuit. In the synchronous circuit, the digital image signals are synchronously processed so as to output horizontal pulses in accordance with a horizontal synchronizing signal contained in the digital image signals and so as to output phase difference information denoting a timing difference between the output of a horizontal pulse and an interpolated crossing of the horizontal synchronizing signal across a synchronizing threshold. A boundary at an image portion and a mask portion of an output image signal is corrected so that the boundary is substantially free of jitter using the horizontal pulses and the phase difference information output by the synchronous circuit. In this manner, a smooth boundary is obtained at the image portion and mask portion of the final compressed image.

8. 发明授权

US06912015B1 Video display apparatus with vertical scan velocity modulation and video display method thereof 失效
标题翻译：具有垂直扫描速度调制的视频显示装置及其视频显示方法
公开(公告)号：US06912015B1
公开(公告)日：2005-06-28
申请号：US09719397
申请日：1999-06-07
申请人： Hideyo Uwabata , Katsumi Terai , Minoru Miyata , Toshiaki Kitahara , Naoji Okumura , Kazuto Tanaka
发明人： Hideyo Uwabata , Katsumi Terai , Minoru Miyata , Toshiaki Kitahara , Naoji Okumura , Kazuto Tanaka
IPC分类号： G09G1/00 , H04N3/30 , H04N3/32 , H04N5/44
CPC分类号： H04N3/30 , H04N3/32
摘要： A parallel scanning circuit outputs a parallel scanning signal for making forward and backward scanning lines parallel. A vertical correlation detection circuit detects a portion where the change in luminance in the vertical direction exceeds a predetermined value on the basis of a luminance signal, and outputs a movement control signal representing the distance of movement on the screen of the scanning line. A retrace period reversion circuit reverses the lime axis of the movement control signal in a retrace period. A clamping circuit clamps the movement control signal to a predetermined DC voltage at the timing of horizontal synchronizing signal. A synthesizing circuit synthesizes the parallel scanning signal and the movement control signal, and feeds a synthesized signal as a vertical velocity modulation signal to a vertical velocity modulation coil.
摘要翻译：并行扫描电路输出用于使前后扫描线平行的并行扫描信号。垂直相关检测电路基于亮度信号检测垂直方向的亮度变化超过预定值的部分，并且在扫描线的屏幕上输出表示移动距离的移动控制信号。回扫周期反转电路在回扫期间反转运动控制信号的石灰轴。钳位电路在水平同步信号的定时将移动控制信号钳位到预定的DC电压。合成电路合成并行扫描信号和移动控制信号，并将合成信号作为垂直速度调制信号馈送到垂直速度调制线圈。

9. 发明授权

US06424383B1 Apparatus for correcting vertical contours 失效
标题翻译：用于校正垂直轮廓的装置
公开(公告)号：US06424383B1
公开(公告)日：2002-07-23
申请号：US09284876
申请日：1999-04-22
申请人： Katsumi Terai , Naoji Okumura , Yutaka Nio , Kazuhito Tanaka
发明人： Katsumi Terai , Naoji Okumura , Yutaka Nio , Kazuhito Tanaka
IPC分类号： H04N521
CPC分类号： H04N5/208
摘要： An object is to provide a vertical contour correcting device for a video signal which reduces noise without deteriorating effect of the entire contour correction. A vertical contour correcting device (VCP1) which corrects vertical contour components (S1v, S1v′) of a video signal (S1) with a given quantity of correction (K) to enhance the vertical contour (Ev) of the video signal (S1) comprises a vertical contour component extracting device (3) for detecting said vertical contour components (S1v, S1v′) from said video signal (S1), a vertical contour component correlation detector (3, 29, 8c, 8d, 4) for detecting correlation between horizontally adjacent vertical contour components (Sb, Sb′, Sb′′) from said detected vertical contour components (S1v, S1v′), and a controller (5) for determining said quantity of correction (K) on the basis of said detected correlation (Sj1), thereby varying the quantity of correction (K) in accordance with the correlation (Sj1).
摘要翻译：一种垂直轮廓校正装置（VCP1），用于校正视频信号的垂直轮廓分量（S1v，S1v'）（垂直轮廓校正装置） S1）具有用于增强视频信号（S1）的垂直轮廓（Ev）的给定量的校正（K）包括垂直轮廓分量提取装置（3），用于从所述垂直轮廓分量（S1v，S1v'）检测所述垂直轮廓分量视频信号（S1），用于检测来自所检测的垂直轮廓分量（S1v）的水平相邻垂直轮廓分量（Sb，Sb'，Sb“）之间的相关性的垂直轮廓分量相关检测器（3,29,8c，8d，4），S1v'），以及控制器（5），用于根据所述检测到的相关（Sj1）确定所述校正量（K），从而根据相关（Sj1）改变校正量（K）。

10. 发明授权

US5715010A Video signal compression apparatus for horizontal compression of a video signal 失效
标题翻译：用于视频信号的水平压缩的视频信号压缩装置
公开(公告)号：US5715010A
公开(公告)日：1998-02-03
申请号：US725075
申请日：1996-10-02
申请人： Yosuke Izawa , Masahiro Tani , Naoji Okumura , Yutaka Nio , Toshichika Sato
发明人： Yosuke Izawa , Masahiro Tani , Naoji Okumura , Yutaka Nio , Toshichika Sato
IPC分类号： H04N5/14 , H04N5/44 , H04N7/01
CPC分类号： H04N7/0122 , H04N5/14 , Y10S348/913
摘要： A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center part of a picture can be horizontally compressed. A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position of the picture can also be changed.
摘要翻译：视频信号压缩装置以每个系统时钟脉冲提取在只读存储器中写入的特定值。每个时钟脉冲可以改变具体值。因此，例如只能将图像的中央部分水平地压缩。可以使用FIFO存储器。可以选择具有固定压缩比的模式或压缩比在每个时钟脉冲下变化的模式。此外，可以从外部设定固定压缩比。图片的显示位置也可以更改。

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