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1. 发明申请

US20080211962A1 FRAME SYNCHRONIZER CIRCUIT 审中-公开
标题翻译：帧同步电路
公开(公告)号：US20080211962A1
公开(公告)日：2008-09-04
申请号：US11960108
申请日：2007-12-19
申请人： Hisaji Murata , Toshihiro Miyoshi , Nariaki Yamamoto
发明人： Hisaji Murata , Toshihiro Miyoshi , Nariaki Yamamoto
IPC分类号： H04N5/04
CPC分类号： H04N7/0105 , H04N5/04 , H04N5/10
摘要： When it is detected that a write address signal and a read address signal coincide with each other during in the judgment range state, an address value of the write address signal is held to halt writing into a memory, whereby a video signal is outputted without mixing old and new frames therein. Therefore, a buffer area in the memory can be minimized, and an address control circuit can be appropriately controlled even when the frame frequency difference exceed a buffer capacity, thereby a frame synchronizer circuit that can output normal pictures is provided.
摘要翻译：当在判断范围状态期间检测到写入地址信号和读取地址信号彼此一致时，写入地址信号的地址值被保持以停止写入存储器，从而在不混合的情况下输出视频信号旧帧和新帧。因此，即使帧频差超过缓冲器容量，也可以使存储器中的缓冲区域最小化，并且可以适当地控制地址控制电路，从而提供能够输出正常图像的帧同步器电路。

2. 发明授权

US06483550B1 Video signal level converting device and video signal analog-to-digital converter 失效
标题翻译：视频信号电平转换器和视频信号模数转换器
公开(公告)号：US06483550B1
公开(公告)日：2002-11-19
申请号：US09320462
申请日：1999-05-27
申请人： Hisaji Murata , Toshihiro Miyoshi
发明人： Hisaji Murata , Toshihiro Miyoshi
IPC分类号： H04N514
CPC分类号： H04N9/64 , H04N5/20 , H04N11/20
摘要： An analog-to-digital converter for converting an analog television signal to a signal in compliance with a digital encoding standard is provided. The analog-to-digital converter according to the invention comprises an A-D converter circuit for converting an analog television signal to a 2n-bit digital signal, a synchronizing signal detecting circuit for detecting a synchronizing signal from the digital signal received from the A-D converter circuit, a Y/C separating circuit for separating a luminance signal and a carrier chrominance signal from the digital signal from the A-D converter circuit using the synchronizing signal from the synchronizing signal detecting circuit, a synchronizing signal converter circuit for converting a synchronizing signal portion of the luminance signal into a predetermined value, and a digital amplifying circuit for digitally amplifying the signal level from the synchronizing signal converter by a predetermined multiple value specified by a standard for communication or for video signal apparatus. The digital amplifying circuit may be composed of a shifter. A low pass filter may be used additionally to eliminate rounding errors. Further, depending on the type of video signal, the low pass filter may be bypassed.
摘要翻译：提供了一种用于将模拟电视信号转换为符合数字编码标准的信号的模拟 - 数字转换器。根据本发明的模数转换器包括用于将模拟电视信号转换为2n位数字信号的AD转换器电路，用于从AD转换器电路接收的数字信号中检测同步信号的同步信号检测电路，用于使用来自同步信号检测电路的同步信号从AD转换器电路的数字信号分离亮度信号和载波色度信号的Y / C分离电路，用于转换来自同步信号检测电路的同步信号部分的同步信号转换器电路亮度信号变为预定值，以及数字放大电路，用于将来自同步信号转换器的信号电平数字放大由通信标准或视频信号装置指定的预定多值。数字放大电路可以由移位器组成。另外可以使用低通滤波器来消除舍入误差。此外，根据视频信号的类型，可以旁路低通滤波器。

3. 发明申请

US20050264697A1 Burst frequency discrimination circuit 审中-公开
标题翻译：突发频率鉴别电路
公开(公告)号：US20050264697A1
公开(公告)日：2005-12-01
申请号：US11133224
申请日：2005-05-20
申请人： Hisaji Murata , Toshihiro Miyoshi
发明人： Hisaji Murata , Toshihiro Miyoshi
IPC分类号： H04N9/00 , H04N9/455 , H04N9/64 , H04N9/65
CPC分类号： H04N9/455
摘要： A picture signal processing circuit capable of processing picture signals of various broadcast systems including the SECAM system, the PAL system and the NTSC system, wherein an FM demodulation circuit for demodulating a SECAM signal is used also as a portion of a burst frequency discrimination circuit. An input picture signal is demodulated by the FM demodulation circuit to obtain a frequency component thereof, and then a burst signal portion thereof is extracted by a burst extracting circuit. The extracted demodulated signal is integrated by an integration circuit, and compared with a predetermined value by a comparator, based on which the burst frequency is determined. Therefore, it is possible to instantaneously determine the burst frequency, and the circuit scale is reduced by sharing the FM demodulation circuit.
摘要翻译：能够处理包括SECAM系统，PAL系统和NTSC系统的各种广播系统的图像信号的图像信号处理电路，其中用于解调SECAM信号的FM解调电路也用作突发频率鉴别电路的一部分。输入图像信号由FM解调电路解调以获得其频率分量，然后由脉冲串提取电路提取其突发信号部分。提取的解调信号由积分电路积分，并且通过比较器与预定值进行比较，基于此确定突发频率。因此，可以瞬间确定突发频率，并且通过共享FM解调电路来减小电路规模。

4. 发明授权

US06724430B2 Sampling frequency converter, sampling frequency conversion method, video signal processor, and video signal processing method 失效
标题翻译：采样变频器，采样频率转换方法，视频信号处理器和视频信号处理方法
公开(公告)号：US06724430B2
公开(公告)日：2004-04-20
申请号：US09820312
申请日：2001-03-29
申请人： Toshihiro Miyoshi , Hisaji Murata , Manabu Yumine
发明人： Toshihiro Miyoshi , Hisaji Murata , Manabu Yumine
IPC分类号： H04N701
CPC分类号： H04N9/89 , H04N9/64
摘要： A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.
摘要翻译：一个DD转换器电路109，用于内插锁定到14.3MHz突发时钟的数字视频信号以将采样数据转换成13.5-NHz的自由运行时钟;以及帧存储器电路110，用于写入包括由DD转换器电路109在14.3MHz突发时钟上输出的数字视频信号以及在13.5MHz时钟S112上读取写入的数字视频信号。因此，可以提供可以在不使用模拟PLL电路的情况下实现数字视频信号的速率转换的视频信号处理器。

5. 发明授权

US06483947B1 Video signal processing apparatus 有权
标题翻译：视频信号处理装置
公开(公告)号：US06483947B1
公开(公告)日：2002-11-19
申请号：US09270531
申请日：1999-03-17
申请人： Ken Yasue , Katsuhisa Yano , Takao Kashiro , Hisaji Murata
发明人： Ken Yasue , Katsuhisa Yano , Takao Kashiro , Hisaji Murata
IPC分类号： G06K936
CPC分类号： H04N19/40 , H04N5/78266 , H04N5/783 , H04N9/8042
摘要： A video signal processing apparatus processes coded data obtained by compressively coding a digitized video signal. The apparatus includes a specific component removing unit for removing specific components in the coded data. The specific component removing unit has a variable-length decoding unit for subjecting the variable-length coded data to variable-length decoding, an inverse quantization unit for inversely quantizing the processing result of the variable-length decoding unit, by using a first quantization matrix, a quantization unit for quantizing the processing result of the inverse quantization unit, by using a second quantization matrix, and a variable-length coding unit for subjecting the processing result of the quantization unit to variable-length coding. Therefore, the data quantity of the variable-length coded data can be reduced without significantly increasing the circuit scale.
摘要翻译：视频信号处理装置处理通过对数字化视频信号进行压缩编码获得的编码数据。该装置包括用于去除编码数据中的特定组件的特定组件去除单元。特定分量去除单元具有用于对可变长度编码数据进行可变长度解码的可变长度解码单元，用于对可变长度解码单元的处理结果进行逆量化的逆量化单元，通过使用第一量化矩阵用于通过使用第二量化矩阵量化逆量化单元的处理结果的量化单元和用于对量化单元的处理结果进行可变长度编码的可变长度编码单元。因此，可以减少可变长度编码数据的数据量而不显着增加电路规模。

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