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1. 发明授权

US06534414B1 Dual-mask etch of dual-poly gate in CMOS processing 失效
标题翻译：双掩模蚀刻CMOS双工多晶硅处理
公开(公告)号：US06534414B1
公开(公告)日：2003-03-18
申请号：US09594328
申请日：2000-06-14
申请人： Kuilong Wang , Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
发明人： Kuilong Wang , Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
IPC分类号： H01L21302
CPC分类号： H01L21/823842
摘要： The invented method involves separately etching the P and N gate features in a dual-poly gate using dual masks, thereby permitting the etching recipes to be tuned to the differentially responsive P and N materials that form the gate. The method involves a) providing a polysilicon layer of a first type over a first region of a semiconductor substrate; b) providing a polysilicon layer of a second type over a second region of the semiconductor substrate; c) depositing a metallic layer overlying the polysilicon layers in the first and second regions; d) depositing an anti-reflective layer overlying the metallic layer in the first and second regions; e) selectively etching the dielectric hard-mask multi-layer film to form a patterned outer hard-mask multi-layer; f) forming a first photoresist pattern overlying the patterned outer hard-mask multi-layer in the first region; g) first etching the metallic layer and the polysilicon layer of the second type to form a stacked gate structure in the second region; h) forming a second photoresist pattern overlying the patterned outer hard-mask multi-layer in the second region; and i) second etching the metallic layer and the polysilicon layer of the first type to form a stacked gate structure in the first region. Preferably, the first photoresist pattern and the second photoresist pattern define a nominal boundary therebetween, with the patterns having a predefined gap therebetween in a region around the boundary. Alternatively, the dual-mask technique is used on a non-hardmask dual-poly film stack and the top dielectric multi-layer film is replaced by an anti-reflection coating (ARC) film.
摘要翻译：本发明的方法涉及使用双掩模单独蚀刻双多晶硅栅极中的P和N栅极特征，从而允许将蚀刻配方调谐到形成栅极的差分响应P和N材料。该方法包括：a）在半导体衬底的第一区域上提供第一类型的多晶硅层; b）在所述半导体衬底的第二区域上提供第二类型的多晶硅层; c）在第一和第二区域中沉积覆盖多晶硅层的金属层; d）在所述第一和第二区域中沉积覆盖所述金属层的抗反射层; e）选择性地蚀刻电介质硬掩模多层膜以形成图案化的外部硬掩模多层; f）在第一区域中形成覆盖图案化的外部硬掩模多层的第一光致抗蚀剂图案; g）首先蚀刻第二类型的金属层和多晶硅层，以在第二区域中形成堆叠栅极结构; h）在所述第二区域中形成覆盖所述图案化的外部硬掩模多层的第二光致抗蚀剂图案; 以及i）第二蚀刻第一类型的金属层和多晶硅层，以在第一区域中形成堆叠栅极结构。优选地，第一光致抗蚀剂图案和第二光致抗蚀剂图案在其之间限定了标称边界，其中图案在边界周围的区域中具有预定的间隙。或者，双掩模技术用于非硬掩模双重多层膜堆叠，并且顶部电介质多层膜被抗反射涂层（ARC）膜替代。

2. 发明授权

US06566236B1 Gate structures with increased etch margin for self-aligned contact and the method of forming the same 失效
标题翻译：具有增加的用于自对准接触的蚀刻余量的栅极结构及其形成方法
公开(公告)号：US06566236B1
公开(公告)日：2003-05-20
申请号：US09558941
申请日：2000-04-26
申请人： Tsengyou Syau , Guo-Qiang (Patrick) Lo , Shih-Ked Lee , Chuen-Der Lien , Sang-Yun Lee , Ching-Kai (Robert) Lin
发明人： Tsengyou Syau , Guo-Qiang (Patrick) Lo , Shih-Ked Lee , Chuen-Der Lien , Sang-Yun Lee , Ching-Kai (Robert) Lin
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/28061 , H01L21/28114 , H01L21/32137
摘要： A novel gate structure and a method of forming the same for a self-aligned contact on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed on the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSix), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is then etched anisotropically down to the first conductive layer along a sidewall approximately vertically aligned with the lower outside corner of the patterned capping layer. The recess has an inward extant from the lower outside corner in a range of between 100-300 Angstroms. Increased etch margin is provided in the gate structure to prevent shorts between contact plugs and gate structures during contact formation.
摘要翻译：一种新颖的栅极结构及其在半导体衬底上形成自对准接触的方法。该方法包括在半导体衬底上形成栅氧化层。然后在栅极氧化物层上形成第一导电层。接下来，形成第二导电层，优选难熔金属硅化物（例如WSix），覆盖在第一导电层上。形成覆盖在第二导电层上的覆盖层。然后对覆盖层进行蚀刻以形成具有较低外角的图案化覆盖层。第二导电层的上部被横向选择性干蚀刻以在覆盖层下方形成横向凹槽以增加蚀刻余量。然后，第二导电层的下部沿着与图案化覆盖层的下部外角大致垂直对准的侧壁各向异性地蚀刻到第一导电层。该凹陷部位在下外角处具有介于100-300埃之间的范围内。在栅极结构中提供增加的蚀刻余量以防止接触形成期间接触插塞和栅极结构之间的短路。

3. 发明授权

US07582567B1 Method for forming CMOS device with self-aligned contacts and region formed using salicide process 有权
标题翻译：用于形成具有自对准触点的CMOS器件的方法和使用自对准硅化物工艺形成的区域
公开(公告)号：US07582567B1
公开(公告)日：2009-09-01
申请号：US11424333
申请日：2006-06-15
申请人： Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
发明人： Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
IPC分类号： H01L21/302
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/823835
摘要： A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.
摘要翻译：公开了一种在半导体衬底上形成CMOS器件的方法，其中栅极结构形成在半导体衬底的芯区域和非芯区域中。栅极结构包括栅极介电层和包括导电层和上覆硬掩模的栅极膜堆叠。然后将硬掩模从非芯区域中的栅极结构移除。然后执行自对准硅化物工艺以在非芯区域中形成硅化物层。形成在芯区域上延伸的阻挡层，并且形成在阻挡层上延伸的预金属介电膜。执行选择性蚀刻工艺以形成延伸穿过预金属介电膜并通过芯区域中的阻挡层的自对准接触开口。然后用导电材料填充这些开口，以在芯区域中形成自对准的触点。这在芯区域产生具有高器件密度的CMOS器件，并且包括非核心区域的高速CMOS器件。

4. 发明授权

US07098114B1 Method for forming cmos device with self-aligned contacts and region formed using salicide process 有权
标题翻译：用自对准接触形成cmos器件的方法和使用自对准硅化物工艺形成的区域
公开(公告)号：US07098114B1
公开(公告)日：2006-08-29
申请号：US10874980
申请日：2004-06-22
申请人： Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
发明人： Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
IPC分类号： H01L21/331
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/823835
摘要： A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.
摘要翻译：公开了一种在半导体衬底上形成CMOS器件的方法，其中栅极结构形成在半导体衬底的芯区域和非芯区域中。栅极结构包括栅极介电层和包括导电层和上覆硬掩模的栅极膜堆叠。然后将硬掩模从非芯区域中的栅极结构移除。然后执行自对准硅化物工艺以在非芯区域中形成硅化物层。形成在芯区域上延伸的阻挡层，并且形成在阻挡层上延伸的预金属介电膜。执行选择性蚀刻工艺以形成延伸穿过预金属介电膜并通过芯区域中的阻挡层的自对准接触开口。然后用导电材料填充这些开口，以在芯区域中形成自对准的触点。这在芯区域产生具有高器件密度的CMOS器件，并且包括非核心区域的高速CMOS器件。

5. 发明授权

US07125783B2 Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean 有权
公开(公告)号：US07125783B2
公开(公告)日：2006-10-24
申请号：US09838084
申请日：2001-04-18
申请人： Guo-Qiang Lo , Ohm-Guo Pan , Zhenjiang Yu , Yu-Lung Mao , Tsengyou Syau , Shih-Ked Lee
发明人： Guo-Qiang Lo , Ohm-Guo Pan , Zhenjiang Yu , Yu-Lung Mao , Tsengyou Syau , Shih-Ked Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/0276 , H01L21/02052 , H01L21/31111 , H01L21/3143 , H01L21/76235 , H01L21/76814 , H01L21/76829 , Y10S438/906 , Y10S438/952
摘要： A method for preventing the formation of watermark defects includes the steps of forming a pad oxide, a silicon nitride layer and a silicon oxynitride layer over a semiconductor substrate. A photoresist mask is formed over the resulting structure, with the silicon oxynitride layer being used as an anti-reflective coating during exposure of the photoresist material. An etch is performed through the photoresist mask, thereby forming a trench in the substrate. The photoresist mask is stripped, and the silicon oxynitride layer is conditioned. For example, the silicon oxynitride layer may be conditioned by a rapid thermal anneal in the presence of oxygen or nitrogen. A wet clean step is subsequently performed to remove a native oxide layer in the trench. The conditioned silicon oxynitride layer prevents the formation of watermarks during the wet clean process.

6. 发明授权

US06306771B1 Process for preventing the formation of ring defects 有权
标题翻译：防止环形缺陷形成的方法
公开(公告)号：US06306771B1
公开(公告)日：2001-10-23
申请号：US09384752
申请日：1999-08-27
申请人： Tsengyou Syau , James R. Shih , Shih-Ked Lee , Timothy P. Kay
发明人： Tsengyou Syau , James R. Shih , Shih-Ked Lee , Timothy P. Kay
IPC分类号： H01L21302
CPC分类号： H01L21/32139 , H01L21/32136
摘要： The prevention of the formation of undesired defects formed during the etching of etched metal interconnect lines on an integrated circuit during an integrated circuit manufacturing process that involves laying down on a semiconductor wafer a thin film such as an anti-reflective coating (ARC) on a layer of metal to be patterned into the metal interconnects of the individual integrated circuits. To do this the anti-reflective coating layer is covered with an oxide layer prior to applying and patterning subsequent photoresist. The specific metalization layer disclosed can be of aluminum, copper or copper-aluminum alloy. The ARC as disclosed is a nitride layer, such as titanium nitride. The oxide may be formed on the ARC in a number of known ways and may be etched subsequently alone or in combination with the underlying ARC and metal after subsequent photoresist deposit upon the oxide layer.
摘要翻译：在集成电路制造过程中防止在集成电路制造过程中在蚀刻金属互连线上的蚀刻金属互连线时形成的不希望的缺陷的形成，其包括在半导体晶片上放置诸如抗反射涂层（ARC）的薄膜金属层将被图案化成各个集成电路的金属互连。为了做到这一点，在施加和图形化随后的光致抗蚀剂之前，抗氧化层被氧化物层覆盖。所公开的具体金属化层可以是铝，铜或铜 - 铝合金。所公开的ARC是氮化物层，例如氮化钛。氧化物可以以多种已知方式形成在ARC上，并且随后光致抗蚀剂沉积在氧化物层上之后可以单独蚀刻或与下面的ARC和金属组合进行蚀刻。

7. 发明授权

US07125775B1 Method for forming hybrid device gates 有权
标题翻译：混合器件门形成方法
公开(公告)号：US07125775B1
公开(公告)日：2006-10-24
申请号：US10805124
申请日：2004-03-18
申请人： Kuilong Wang , Tsengyou Syau , Jeong Choi
发明人： Kuilong Wang , Tsengyou Syau , Jeong Choi
IPC分类号： H01L21/336
CPC分类号： H01L21/32139 , H01L21/823828 , H01L21/82385 , H01L27/1052
摘要： A method for forming self-aligned contact devices in a core region of a semiconductor substrate and non-self-aligned contact devices in a non-core region of the semiconductor substrate is disclosed in which a single gate film stack is used for forming gate structures in both the core region and in the non-core region. A dielectric layer is formed over a semiconductor substrate and a gate film stack is formed over the dielectric layer. The gate film stack is then patterned so as to form gate structures within both the core region and the non-core region.
摘要翻译：公开了一种用于在半导体衬底的芯区域中形成自对准接触器件和在半导体衬底的非芯区域中的非自对准接触器件的方法，其中使用单个栅极膜堆叠来形成栅极结构在核心区域和非核心区域。在半导体衬底上形成介电层，并且在电介质层上形成栅极膜叠层。然后对栅极膜堆叠进行图案化，以便在芯部区域和非芯部区域内形成栅极结构。

8. 发明授权

US07037774B1 Self-aligned contact structure and process for forming self-aligned contact structure 有权
标题翻译：自对准接触结构和形成自对准接触结构的工艺
公开(公告)号：US07037774B1
公开(公告)日：2006-05-02
申请号：US10970074
申请日：2004-10-21
申请人： Tsengyou Syau
发明人： Tsengyou Syau
IPC分类号： H01L21/8238
CPC分类号： H01L21/76895 , H01L21/76816 , H01L21/76832 , H01L21/76897 , H01L21/823871
摘要： A CMOS structure and a process for forming CMOS devices are disclosed in which gate film stacks are formed over a semiconductor substrate. A barrier layer and a first dielectric film are formed such that they extend over the gate film stacks. Metal lines are formed over the pre-metal dielectric film and spacers are formed that extend on opposite sides of the metal lines. A second dielectric film is formed that extends over the metal lines. A masking structure is formed that defines a contact opening. Selective etch processes are performed to form a self-aligned contact opening, with the adjacent metal lines and spacers aligning the self-aligned contact opening between adjacent gate film stacks. A metal layer is then deposited and planarized to form a self-aligned contact. The masking structure can also define additional contact openings, which are simultaneously etched and filled with metal to form borderless, strapped and shared contacts. These borderless contacts, contacts and shared contacts can either be aligned on one side or can be positioned using only the masking structure.
摘要翻译：公开了CMOS结构和用于形成CMOS器件的工艺，其中在半导体衬底上形成栅极膜堆叠。形成阻挡层和第一电介质膜，使得它们在栅极膜堆叠上延伸。金属线形成在预金属电介质膜上，并且形成在金属线的相对侧上延伸的间隔物。形成在金属线上延伸的第二电介质膜。形成限定接触开口的掩模结构。执行选择性蚀刻处理以形成自对准接触开口，其中相邻的金属线和间隔件对准相邻栅极膜堆叠之间的自对准接触开口。然后沉积金属层并平坦化以形成自对准接触。掩模结构还可以限定额外的接触开口，其同时被蚀刻并用金属填充以形成无边界，带状和共享的触点。这些无边界触点，触点和共享触点可以在一侧对齐，也可以仅使用掩模结构定位。

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