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US06566236B1 Gate structures with increased etch margin for self-aligned contact and the method of forming the same 失效
标题翻译：具有增加的用于自对准接触的蚀刻余量的栅极结构及其形成方法
公开(公告)号：US06566236B1
公开(公告)日：2003-05-20
申请号：US09558941
申请日：2000-04-26
申请人： Tsengyou Syau , Guo-Qiang (Patrick) Lo , Shih-Ked Lee , Chuen-Der Lien , Sang-Yun Lee , Ching-Kai (Robert) Lin
发明人： Tsengyou Syau , Guo-Qiang (Patrick) Lo , Shih-Ked Lee , Chuen-Der Lien , Sang-Yun Lee , Ching-Kai (Robert) Lin
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/28061 , H01L21/28114 , H01L21/32137
摘要： A novel gate structure and a method of forming the same for a self-aligned contact on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed on the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSix), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is then etched anisotropically down to the first conductive layer along a sidewall approximately vertically aligned with the lower outside corner of the patterned capping layer. The recess has an inward extant from the lower outside corner in a range of between 100-300 Angstroms. Increased etch margin is provided in the gate structure to prevent shorts between contact plugs and gate structures during contact formation.
摘要翻译：一种新颖的栅极结构及其在半导体衬底上形成自对准接触的方法。该方法包括在半导体衬底上形成栅氧化层。然后在栅极氧化物层上形成第一导电层。接下来，形成第二导电层，优选难熔金属硅化物（例如WSix），覆盖在第一导电层上。形成覆盖在第二导电层上的覆盖层。然后对覆盖层进行蚀刻以形成具有较低外角的图案化覆盖层。第二导电层的上部被横向选择性干蚀刻以在覆盖层下方形成横向凹槽以增加蚀刻余量。然后，第二导电层的下部沿着与图案化覆盖层的下部外角大致垂直对准的侧壁各向异性地蚀刻到第一导电层。该凹陷部位在下外角处具有介于100-300埃之间的范围内。在栅极结构中提供增加的蚀刻余量以防止接触形成期间接触插塞和栅极结构之间的短路。

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