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1. 发明授权

US06534414B1 Dual-mask etch of dual-poly gate in CMOS processing 失效
标题翻译：双掩模蚀刻CMOS双工多晶硅处理
公开(公告)号：US06534414B1
公开(公告)日：2003-03-18
申请号：US09594328
申请日：2000-06-14
申请人： Kuilong Wang , Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
发明人： Kuilong Wang , Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
IPC分类号： H01L21302
CPC分类号： H01L21/823842
摘要： The invented method involves separately etching the P and N gate features in a dual-poly gate using dual masks, thereby permitting the etching recipes to be tuned to the differentially responsive P and N materials that form the gate. The method involves a) providing a polysilicon layer of a first type over a first region of a semiconductor substrate; b) providing a polysilicon layer of a second type over a second region of the semiconductor substrate; c) depositing a metallic layer overlying the polysilicon layers in the first and second regions; d) depositing an anti-reflective layer overlying the metallic layer in the first and second regions; e) selectively etching the dielectric hard-mask multi-layer film to form a patterned outer hard-mask multi-layer; f) forming a first photoresist pattern overlying the patterned outer hard-mask multi-layer in the first region; g) first etching the metallic layer and the polysilicon layer of the second type to form a stacked gate structure in the second region; h) forming a second photoresist pattern overlying the patterned outer hard-mask multi-layer in the second region; and i) second etching the metallic layer and the polysilicon layer of the first type to form a stacked gate structure in the first region. Preferably, the first photoresist pattern and the second photoresist pattern define a nominal boundary therebetween, with the patterns having a predefined gap therebetween in a region around the boundary. Alternatively, the dual-mask technique is used on a non-hardmask dual-poly film stack and the top dielectric multi-layer film is replaced by an anti-reflection coating (ARC) film.
摘要翻译：本发明的方法涉及使用双掩模单独蚀刻双多晶硅栅极中的P和N栅极特征，从而允许将蚀刻配方调谐到形成栅极的差分响应P和N材料。该方法包括：a）在半导体衬底的第一区域上提供第一类型的多晶硅层; b）在所述半导体衬底的第二区域上提供第二类型的多晶硅层; c）在第一和第二区域中沉积覆盖多晶硅层的金属层; d）在所述第一和第二区域中沉积覆盖所述金属层的抗反射层; e）选择性地蚀刻电介质硬掩模多层膜以形成图案化的外部硬掩模多层; f）在第一区域中形成覆盖图案化的外部硬掩模多层的第一光致抗蚀剂图案; g）首先蚀刻第二类型的金属层和多晶硅层，以在第二区域中形成堆叠栅极结构; h）在所述第二区域中形成覆盖所述图案化的外部硬掩模多层的第二光致抗蚀剂图案; 以及i）第二蚀刻第一类型的金属层和多晶硅层，以在第一区域中形成堆叠栅极结构。优选地，第一光致抗蚀剂图案和第二光致抗蚀剂图案在其之间限定了标称边界，其中图案在边界周围的区域中具有预定的间隙。或者，双掩模技术用于非硬掩模双重多层膜堆叠，并且顶部电介质多层膜被抗反射涂层（ARC）膜替代。

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