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1. 发明授权

US5955227A Pattern determination method 失效
标题翻译：模式确定方法
公开(公告)号：US5955227A
公开(公告)日：1999-09-21
申请号：US89492
申请日：1998-06-02
申请人： Kouichirou Tsujita , Junjiro Sakai , Akihiro Nakae
发明人： Kouichirou Tsujita , Junjiro Sakai , Akihiro Nakae
IPC分类号： G03F7/26 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F7/705
摘要： A pattern determination method includes a step for setting an interconnection width and the like, a step for representing the mask pattern and aperture configuration in functions, steps for calculating amplitude distribution of exposure light, a step for calculating intensity distribution of exposure light at an image plane, steps for calculating maximum, minimum, and reference intensity of exposure light, a step for determining exposure margin and focus margin, a step for storing data of qualification/disqualification of optical image formation, and a step for providing a display of a table. A configuration including four openings is set for the aperture. Determination of whether an optical image of an interconnection pattern can be formed or not is facilitated by the table in setting the interconnection pattern of a semiconductor device.
摘要翻译：图案确定方法包括设置互连宽度等的步骤，用于表示功能中的掩模图案和孔径配置的步骤，用于计算曝光光的幅度分布的步骤，用于计算图像上的曝光光的强度分布的步骤平面，用于计算曝光光的最大，最小和参考强度的步骤，用于确定曝光余量和聚焦余量的步骤，存储光学图像形成的资格/取消资格数据的步骤，以及用于提供表格显示的步骤。为孔径设置包括四个开口的构造。通过设置半导体器件的互连图案的方便，能够确定是否可以形成布线图案的光学图像。

2. 发明授权

US06607992B2 Antireflection coating and semiconductor device manufacturing method 有权
公开(公告)号：US06607992B2
公开(公告)日：2003-08-19
申请号：US09955100
申请日：2001-09-19
申请人： Kouichirou Tsujita , Atsumi Yamaguchi , Junjiro Sakai , Kouji Oda , Koichiro Narimatsu
发明人： Kouichirou Tsujita , Atsumi Yamaguchi , Junjiro Sakai , Kouji Oda , Koichiro Narimatsu
IPC分类号： H01L2131
CPC分类号： H01L21/76832 , G03F7/091 , H01L21/28123 , H01L21/3081 , H01L21/31144 , H01L21/32139 , H01L21/76808 , H01L21/76897 , H01L2924/0002 , Y10T428/252 , Y10T428/254 , Y10T428/31982 , H01L2924/00
摘要： An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.

3. 发明授权

US06898851B2 Electronic device manufacturing method 失效
标题翻译：电子元件制造方法
公开(公告)号：US06898851B2
公开(公告)日：2005-05-31
申请号：US10717718
申请日：2003-11-21
申请人： Yasutaka Nishioka , Junjiro Sakai , Shingo Tomohisa , Susumu Matsumoto , Fumio Iwamoto , Michinari Yamanaka
发明人： Yasutaka Nishioka , Junjiro Sakai , Shingo Tomohisa , Susumu Matsumoto , Fumio Iwamoto , Michinari Yamanaka
IPC分类号： H01K3/10 , H01L21/768 , H05K3/10
CPC分类号： H01L21/76808 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165
摘要： It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.
摘要翻译：本发明的目的是提供一种具有掩埋多层布线结构的半导体器件，其中抗蚀剂图案的分辨率缺陷的产生被抑制，并且由分辨率缺陷引起的缺陷布线的产生减少。在形成到达蚀刻停止膜（4）的通孔（7）之后，在通孔（7）打开的情况下，在300〜400℃进行退火。作为退火方法，可以使用使用热板的方法和使用热处理炉的方法。为了抑制对制造的下布线（20）的影响，通过使用热板进行约5〜10分钟的短时间的加热。因此，残留在上部保护膜（6）和具有低介电常数的副产物残留在蚀刻阻挡膜（4）的界面上的层间电介质膜（5）的界面中的副产物和排出具有低介电常数的层间绝缘膜（5），从而可以减少残留副产物的量。

4. 发明授权

US08119308B2 Photomask, apparatus for manufacturing semiconductor device having the photomask, and method of manufacturing semiconductor device using the photomask 有权
标题翻译：光掩模，具有光掩模的半导体装置的制造装置以及使用该光掩模的半导体装置的制造方法
公开(公告)号：US08119308B2
公开(公告)日：2012-02-21
申请号：US12394296
申请日：2009-02-27
申请人： Ayumi Minamide , Akemi Moniwa , Junjiro Sakai , Manabu Ishibashi
发明人： Ayumi Minamide , Akemi Moniwa , Junjiro Sakai , Manabu Ishibashi
IPC分类号： G03F1/00
CPC分类号： G03F1/36 , Y10T29/41
摘要： A photomask is disclosed which can suppress deterioration of the depth of focus even in the case where main features are arranged randomly. Sub-features are replaced by a quadrangular sub-feature located inside an external quadrangle which includes as part of its outer periphery the outermost portions of the original sub-features. The sub-feature after the replacement is preferably in a square shape and the length of one side thereof is determined in accordance with the length of the associated external quadrangle. A central position of the sub-feature after the replacement is preferably coincident with the center of the external quadrangle or the center of gravity of the region which includes the original sub-features.
摘要翻译：公开了即使在主要特征被随机排列的情况下也可以抑制焦深的劣化的光掩模。子特征由位于外部四边形内部的四边形子特征代替，其包括作为其外周边的一部分的原始子特征的最外部分。更换后的子特征优选为正方形，其一侧的长度根据相关的外部四边形的长度确定。替换之后的子特征的中心位置优选地与外部四边形的中心或包括原始子特征的区域的重心重合。

5. 发明申请

US20090239159A1 PHOTOMASK, APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING THE PHOTOMASK, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE PHOTOMASK 有权
标题翻译： PHOTOMASK，用于制造具有光电子的半导体器件的装置，以及使用光电子器件制造半导体器件的方法
公开(公告)号：US20090239159A1
公开(公告)日：2009-09-24
申请号：US12394296
申请日：2009-02-27
申请人： Ayumi MINAMIDE , Akemi Moniwa , Junjiro Sakai , Manabu Ishibashi
发明人： Ayumi MINAMIDE , Akemi Moniwa , Junjiro Sakai , Manabu Ishibashi
IPC分类号： G03F1/14 , G03F1/00 , G03F7/20 , H01L21/00
CPC分类号： G03F1/36 , Y10T29/41
摘要： A photomask is disclosed which can suppress deterioration of the depth of focus even in the case where main features are arranged randomly. Sub-features are replaced by a quadrangular sub-feature located inside an external quadrangle which includes as part of its outer periphery the outermost portions of the original sub-features. The sub-feature after the replacement is preferably in a square shape and the length of one side thereof is determined in accordance with the length of the associated external quadrangle. A central position of the sub-feature after the replacement is preferably coincident with the center of the external quadrangle or the center of gravity of the region which includes the original sub-features.
摘要翻译：公开了即使在主要特征被随机排列的情况下也可以抑制焦深的劣化的光掩模。子特征由位于外部四边形内部的四边形子特征代替，其包括作为其外周边的一部分的原始子特征的最外部分。更换后的子特征优选为正方形，其一侧的长度根据相关的外部四边形的长度确定。替换之后的子特征的中心位置优选地与外部四边形的中心或包括原始子特征的区域的重心重合。

6. 发明授权

US07030007B2 Via-filling material and process for fabricating semiconductor integrated circuit using the material 失效
标题翻译：通孔填充材料和使用该材料的半导体集成电路的制造工艺
公开(公告)号：US07030007B2
公开(公告)日：2006-04-18
申请号：US10623772
申请日：2003-07-22
申请人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
发明人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
IPC分类号： H01L21/47
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/312 , H01L21/3127 , H01L21/76814
摘要： A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(═O)O— or —S(═O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.
摘要翻译：通孔填充材料包括含有由氢，氟，氯，溴和甲基中的R 1〜1个表示的重复单元的聚合物; R 2是氢，C 1-3烷基和被取代氢的C 1-4烷基中的一个通过氟，氯和溴中的至少一种; 并且X是-C（-O）O-或-S（-O）2 O-。这种通孔填充材料在等离子体蚀刻期间不会在通孔的开口附近产生沉积物，并且提供具有高可靠性的半导体集成电路，即使当通过等离子体蚀刻形成通孔以外的沟槽时，通孔周围填充有通孔通孔填充材料。

7. 发明申请

US20050101123A1 Via-filling material and process for fabricating semiconductor integrated circuit using the material 失效
标题翻译：通孔填充材料和使用该材料制造半导体集成电路的工艺
公开(公告)号：US20050101123A1
公开(公告)日：2005-05-12
申请号：US10623772
申请日：2003-07-22
申请人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
发明人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
IPC分类号： C08L33/04 , C08F20/22 , C08L63/00 , H01L21/311 , H01L21/312 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/312 , H01L21/3127 , H01L21/76814
摘要： A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(═O)O or —S(═O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.
摘要翻译：通孔填充材料包括含有由氢，氟，氯，溴和甲基中的R 1〜1个表示的重复单元的聚合物; R 2是氢，C 1-3烷基和被取代氢的C 1-4烷基中的一个通过氟，氯和溴中的至少一种; 并且X是-C（-O）O或-S（-O）2 O-。这种通孔填充材料在等离子体蚀刻期间不会在通孔的开口附近产生沉积物，并且提供具有高可靠性的半导体集成电路，即使当通过等离子体蚀刻形成通孔以外的沟槽时，通孔周围填充有通孔通孔填充材料。

8. 发明授权

US08129078B2 Mask, method for manufacturing the same, and method for manufacturing semiconductor device 有权
标题翻译：掩模，其制造方法以及半导体器件的制造方法
公开(公告)号：US08129078B2
公开(公告)日：2012-03-06
申请号：US12716665
申请日：2010-03-03
申请人： Akira Imai , Junjiro Sakai
发明人： Akira Imai , Junjiro Sakai
IPC分类号： G03F1/00 , G03C5/00
CPC分类号： G03F1/36 , H01L29/6659
摘要： A mask having mask patterns for the transfer of a desired circuit pattern, a method for manufacturing the mask, and a semiconductor device manufacturing method using the mask, are provided. There are extracted two rectangular aperture patterns which are adjacent each other in an obliquely disposed state with respect to an X axis in an XY plane. The thus-extracted two rectangular aperture patterns are rotated at a certain angle so that a pattern edge corresponding to one side of one of the rectangular aperture patterns and a pattern edge corresponding to one side of the other rectangular aperture pattern are opposed in parallel to each other. The two rectangular aperture patterns thus rotated at a certain angle are then subjected to optical proximity effect correction to form two corrected rectangular aperture patterns.
摘要翻译：提供了具有用于传送期望电路图案的掩模图案的掩模，用于制造掩模的方法以及使用该掩模的半导体器件制造方法。提取两个相对于XY平面中的X轴倾斜布置的状态彼此相邻的矩形孔径图案。由此提取的两个矩形孔径图案以一定角度旋转，使得对应于一个矩形孔图案的一侧的图案边缘和对应于另一个矩形孔图案的一侧的图案边缘平行于每个其他。然后以一定角度旋转的两个矩形孔径图案经受光学邻近效应校正以形成两个校正的矩形孔径图案。

9. 发明申请

US20100227444A1 MASK, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：掩模，其制造方法和制造半导体器件的方法
公开(公告)号：US20100227444A1
公开(公告)日：2010-09-09
申请号：US12716665
申请日：2010-03-03
申请人： Akira Imai , Junjiro Sakai
发明人： Akira Imai , Junjiro Sakai
IPC分类号： H01L21/336 , G03F1/00
CPC分类号： G03F1/36 , H01L29/6659
摘要： A mask having mask patterns for the transfer of a desired circuit pattern, a method for manufacturing the mask, and a semiconductor device manufacturing method using the mask, are provided. There are extracted two rectangular aperture patterns which are adjacent each other in an obliquely disposed state with respect to an X axis in an XY plane. The thus-extracted two rectangular aperture patterns are rotated at a certain angle so that a pattern edge corresponding to one side of one of the rectangular aperture patterns and a pattern edge corresponding to one side of the other rectangular aperture pattern are opposed in parallel to each other. The two rectangular aperture patterns thus rotated at a certain angle are then subjected to optical proximity effect correction to form two corrected rectangular aperture patterns.
摘要翻译：提供了具有用于传送期望电路图案的掩模图案的掩模，用于制造掩模的方法以及使用该掩模的半导体器件制造方法。提取两个相对于XY平面中的X轴倾斜布置的状态彼此相邻的矩形孔径图案。由此提取的两个矩形孔径图案以一定角度旋转，使得对应于一个矩形孔图案的一侧的图案边缘和对应于另一个矩形孔图案的一侧的图案边缘平行于每个其他。然后以一定角度旋转的两个矩形孔径图案经受光学邻近效应校正以形成两个校正的矩形孔径图案。

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