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1. 发明授权

US06667505B2 Semiconductor device having a plurality of capacitors aligned at regular intervals 有权
标题翻译：具有以规则间隔对准的多个电容器的半导体器件
公开(公告)号：US06667505B2
公开(公告)日：2003-12-23
申请号：US10123165
申请日：2002-04-17
申请人： Koichiro Narimatsu , Shigeru Shiratake
发明人： Koichiro Narimatsu , Shigeru Shiratake
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L27/0207 , H01L28/90
摘要： A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.
摘要翻译：半导体器件包括形成为具有大致椭圆形横截面形状并从每个所述存储节点接触件的上表面向上延伸的电容器。当从上方观察电容器的布置时，形成电容器行，使得沿着近似椭圆的长轴的方向，多个电容器以规则的间隔对准。当将所述电容器行中的任意一个作为第一电容器行时，与其并联布置第二电容器行，并且第一电容器行和第二电容器行中的电容器彼此相位相差大约对应的长度到一个传输门的宽度和传输门之间的一个空间的宽度之和。

2. 发明授权

US06607992B2 Antireflection coating and semiconductor device manufacturing method 有权
公开(公告)号：US06607992B2
公开(公告)日：2003-08-19
申请号：US09955100
申请日：2001-09-19
申请人： Kouichirou Tsujita , Atsumi Yamaguchi , Junjiro Sakai , Kouji Oda , Koichiro Narimatsu
发明人： Kouichirou Tsujita , Atsumi Yamaguchi , Junjiro Sakai , Kouji Oda , Koichiro Narimatsu
IPC分类号： H01L2131
CPC分类号： H01L21/76832 , G03F7/091 , H01L21/28123 , H01L21/3081 , H01L21/31144 , H01L21/32139 , H01L21/76808 , H01L21/76897 , H01L2924/0002 , Y10T428/252 , Y10T428/254 , Y10T428/31982 , H01L2924/00
摘要： An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.

3. 发明授权

US5991007A Step and scan exposure system and semiconductor device manufactured using said system 失效
标题翻译：使用所述系统制造的步进扫描曝光系统和半导体器件
公开(公告)号：US5991007A
公开(公告)日：1999-11-23
申请号：US965039
申请日：1997-11-05
申请人： Koichiro Narimatsu
发明人： Koichiro Narimatsu
IPC分类号： G03F7/20 , G03F7/207 , G03F9/00 , H01L21/00 , H01L21/027 , G03B27/42 , G03B27/54
CPC分类号： G03F7/70358 , G03F9/70 , H01L21/00
摘要： A step and scan exposure system projects a reticle image onto a semiconductor wafer mounted on a semiconductor wafer stage by a projection optical system in a slit scan scheme, focusing illumination light on the semiconductor wafer to form a plurality of focus sense areas arranged in a direction perpendicular to a scanning direction, receiving reflected illumination light by a plurality of photodetectors, and controlling the wafer stage by the signals from the plurality of photodetectors. In one embodiment, the signals from the plurality of photodetectors are selected, for controlling the wafer stage, corresponding to designated regions for focusing on the semiconductor wafer.
摘要翻译：步进扫描曝光系统通过投影光学系统以狭缝扫描方案将掩模版图像投影到安装在半导体晶片台上的半导体晶片上，将照明光聚焦在半导体晶片上，以形成沿着方向布置的多个焦点感测区域垂直于扫描方向，通过多个光电检测器接收反射的照明光，并且通过来自多个光电检测器的信号来控制晶片台。在一个实施例中，选择来自多个光电检测器的信号，用于控制对应于用于聚焦在半导体晶片上的指定区域的晶片台。

4. 发明授权

US5869906A Registration accuracy measurement mark for semiconductor devices 失效
标题翻译：半导体器件的注册精度测量标记
公开(公告)号：US5869906A
公开(公告)日：1999-02-09
申请号：US851471
申请日：1997-05-05
申请人： Koichiro Narimatsu
发明人： Koichiro Narimatsu
IPC分类号： H01L21/66 , G03F7/20 , H01L21/027 , H01L23/544 , H05K1/02 , B32B5/16
CPC分类号： G03F7/70633 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10T428/24802 , Y10T428/24917
摘要： A registration accuracy measurement mark has a first measurement mark, a second measurement mark, and a third measurement mark arranged in different layers in a layered manner. The first measurement mark includes a first sidewall and a second sidewall in parallel along a Y direction. The second measurement mark includes a third sidewall and a fourth sidewall in parallel along an X direction. The third measurement mark includes a fifth sidewall and a sixth sidewall in parallel along the X direction, and a seventh sidewall and an eighth sidewall in parallel along the Y direction. Registration accuracy measurement in both the X and Y directions can be carried out at the same time even when the measurement of registration accuracy in the X and Y directions respectively is directed to different layers.
摘要翻译：登记精度测量标记具有以分层方式布置在不同层中的第一测量标记，第二测量标记和第三测量标记。第一测量标记包括沿Y方向平行的第一侧壁和第二侧壁。第二测量标记包括沿X方向平行的第三侧壁和第四侧壁。第三测量标记包括沿X方向平行的第五侧壁和第六侧壁，以及沿Y方向平行的第七侧壁和第八侧壁。即使X和Y方向的配准精度的测量分别针对不同的层，也可以同时进行X方向和Y方向的配准精度测量。

5. 发明授权

US5892291A Registration accuracy measurement mark 失效
标题翻译：注册精度测量标记
公开(公告)号：US5892291A
公开(公告)日：1999-04-06
申请号：US670313
申请日：1996-06-27
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： G03F1/36 , G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027 , H05K1/02 , H01L23/544
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

6. 发明授权

US6114072A Reticle having interlocking dicing regions containing monitor marks and exposure method and apparatus utilizing same 失效
标题翻译：具有包含监视标记的互锁切割区域的掩模版和利用其的曝光方法和装置
公开(公告)号：US6114072A
公开(公告)日：2000-09-05
申请号：US100091
申请日：1998-06-19
申请人： Koichiro Narimatsu
发明人： Koichiro Narimatsu
IPC分类号： G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027
CPC分类号： G03F7/70633 , G03F1/42 , G03F9/70
摘要： On one of opposing sides of a rectangular prescribed region consisting of element forming regions and a dicing region placed therebetween, a dicing region is formed to have recessed and extended portions which fit recessed and extended portions of another dicing region which is arranged on the other one of the opposing sides. At extended portions of the dicing region, monitor mark regions are arranged corresponding to all four corners of the prescribed region. Therefore, a reticle which can prevent degradation in registration accuracy caused by shot rotation error or shot magnification error without increasing area of the dicing region is provided, and further, method and apparatus for exposure using the reticle are provided.
摘要翻译：在由元件形成区域和设置在其间的切割区域构成的矩形规定区域的相对侧中的一个上，形成具有凹入和延伸部分的切割区域，该凹陷部分和延伸部分配置在另一个上的另一个切割区域的凹进和延伸部分的对面。在切割区域的延伸部分，监视标记区域对应于规定区域的所有四个角度排列。因此，提供了可以防止由于射击旋转误差或射出倍率误差引起的配准精度降低而不增加切割区域的面积的掩模版，并且还提供了使用掩模版的曝光方法和装置。

7. 发明授权

US06849957B2 Photomask including auxiliary mark area, semiconductor device and manufacturing method thereof 有权
标题翻译：包括辅助标记区域的光掩模，半导体器件及其制造方法
公开(公告)号：US06849957B2
公开(公告)日：2005-02-01
申请号：US09725853
申请日：2000-11-30
申请人： Masahiko Takeuchi , Koichiro Narimatsu , Atsushi Ueno
发明人： Masahiko Takeuchi , Koichiro Narimatsu , Atsushi Ueno
IPC分类号： H01L21/66 , G03F9/00 , H01L21/027 , H01L21/822 , H01L23/544 , H01L27/04
CPC分类号： G03F9/7084 , G03F1/42 , G03F9/7076 , H01L23/544 , H01L2223/54406 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device enabling precise and accurate measurement of an inspection mark in a simple manner is obtained. The semiconductor device includes a device forming area and a dicing line area arranged to surround the device forming area on a semiconductor substrate. In the dicing line area, first and second registration marks formed in different shots are provided, and the first and second registration marks include auxiliary marks for identifying the first and second registration marks.
摘要翻译：获得能够以简单的方式精确而准确地测量检查标记的半导体器件。半导体器件包括设置成围绕半导体衬底上的器件形成区域的器件形成区域和切割线区域。在切割线区域中，设置以不同镜头形成的第一和第二对准标记，并且第一和第二对准标记包括用于识别第一和第二对准标记的辅助标记。

8. 发明授权

US06596603B1 Semiconductor device and manufacturing method thereof, and registration accuracy measurement enhancement method 失效
标题翻译：半导体器件及其制造方法，以及配准精度测量增强方法
公开(公告)号：US06596603B1
公开(公告)日：2003-07-22
申请号：US09570463
申请日：2000-05-12
申请人： Koichiro Narimatsu
发明人： Koichiro Narimatsu
IPC分类号： H01L2176
CPC分类号： G03F7/706 , G03F7/70633 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A semiconductor device with an enhanced registration accuracy photo-mask used for manufacturing the device and a registration accuracy enhancement method are provided, by detecting lens aberration which causes problems in the process of manufacturing a semiconductor device. The semiconductor device includes an auxiliary mark including an inner mark having stepped portions with four sides as stepped portions to be detected and an outer mark having stepped portion as stepped portions to be detected, provided approximately parallel to stepped portions along four sides of the inner mark.
摘要翻译：通过检测在制造半导体器件的过程中出现问题的透镜像差，提供具有用于制造器件的增强的配准精度光掩模和配准精度提高方法的半导体器件。半导体器件包括辅助标记，该辅助标记包括具有台阶部分的内部标记，其中四边为待检测的阶梯部分，外部标记具有台阶部分作为要检测的阶梯部分，大致平行于内标记四边的阶梯部分。

9. 发明授权

US06943458B2 Semiconductor device and manufacturing method thereof, and registration accuracy measurement enhancement method 失效
标题翻译：半导体器件及其制造方法，以及配准精度测量增强方法
公开(公告)号：US06943458B2
公开(公告)日：2005-09-13
申请号：US10603738
申请日：2003-06-26
申请人： Koichiro Narimatsu
发明人： Koichiro Narimatsu
IPC分类号： H01L21/027 , G03F1/42 , G03F1/44 , G03F7/20 , G03F9/00 , H01L23/544
CPC分类号： G03F7/706 , G03F7/70633 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A semiconductor device with an enhanced registration accuracy photo-mask used for manufacturing the device and a registration accuracy enhancement method are provided, by detecting lens aberration which causes problems in the process of manufacturing a semiconductor device. The semiconductor device includes an auxiliary mark including an inner mark having stepped portions with four sides as stepped portions to be detected and an outer mark having stepped portion as stepped portions to be detected, provided approximately parallel to stepped portions along four sides of the inner mark.
摘要翻译：通过检测在制造半导体器件的过程中出现问题的透镜像差，提供具有用于制造器件的增强的配准精度光掩模和配准精度提高方法的半导体器件。半导体器件包括辅助标记，该辅助标记包括具有台阶部分的内部标记，其中四边为待检测的阶梯部分，外部标记具有台阶部分作为要检测的阶梯部分，大致平行于内标记四边的阶梯部分。

10. 发明授权

US06323560B1 Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photo mask and method of exposure thereof 有权
标题翻译：注册精度测量标记，修理标记缺陷的方法，具有标记的光掩模，制造光掩模的方法及其曝光方法
公开(公告)号：US06323560B1
公开(公告)日：2001-11-27
申请号：US09492750
申请日：2000-01-27
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： H01L2358
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

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