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1. 发明授权

US5867253A Method of correcting light proximity effect 失效
标题翻译：校正光接近效应的方法
公开(公告)号：US5867253A
公开(公告)日：1999-02-02
申请号：US800903
申请日：1997-02-12
申请人： Akihiro Nakae
发明人： Akihiro Nakae
IPC分类号： G03F1/36 , G03F1/68 , G03F7/20 , H01L21/027 , G03B27/54
CPC分类号： G03F7/70441
摘要： According to a method of correcting light proximity effect, a decision distance from one exposure point to the other exposure point, where influence of the light proximity effect appears, as well as a reference area ratio for deciding as to whether the light proximity effect correction is necessary or not are determined based on an optical condition of an exposure apparatus having a photomask attached thereto. Respective sides of a photomask pattern are divided into portions each having at most a prescribed length, and a ratio of an area occupied by the photomask pattern to an area of a circle having a middle point of each divided side as a center and the decision distance as a radius is determined for each of the divided sides. Comparing the area ratio for each of the divided sides with the reference area ratio for decision, a decision is made for each divided side as to whether the light proximity effect correction is necessary or not. Using this method, time required for calculation can be reduced, and highly precise correction can be made.
摘要翻译：根据校正光接近效应的方法，出现光接近效应的影响的一个曝光点到另一曝光点的判定距离以及用于判定光接近效应校正是否为根据具有安装有光掩模的曝光装置的光学条件来确定是否需要。光掩模图案的各个侧面被分成最多具有规定长度的部分，并且由光掩模图案占据的区域与以每个分割边的中点为中心的圆的区域的比例以及判定距离因为对于每个分割侧确定半径。将每个分割边的面积比与参考面积比进行比较以作出决定，对于每个分割侧是否需要光接近效应校正，作出判断。使用该方法，可以减少计算所需的时间，并且可以进行高精度的校正。

2. 发明授权

US6048647A Phase shift mask of attenuation type and manufacturing method thereof 失效
标题翻译：衰减类型的相移掩模及其制造方法
公开(公告)号：US6048647A
公开(公告)日：2000-04-11
申请号：US965402
申请日：1997-11-07
申请人： Junji Miyazaki , Akihiro Nakae , Nobuyuki Yoshioka , Hidehiko Kozawa
发明人： Junji Miyazaki , Akihiro Nakae , Nobuyuki Yoshioka , Hidehiko Kozawa
IPC分类号： G03F1/68 , G03F1/00 , G03F1/26 , G03F1/29 , G03F1/32 , G03F1/36 , G03F1/80 , H01L21/027 , G03F1/08
CPC分类号： G03F1/32 , G03F1/26 , G03F1/36
摘要： In accordance with a phase shift mask of attenuation type and a manufacturing method thereof, at a prescribed region of a phase shifter portion near and around a light transmitting portion, an auxiliary pattern is provided for controlling an amount of exposure light onto a portion of an exposed material corresponding to this region. Auxiliary pattern enables to cancel light intensity of a side lobe, thereby preventing generation of a region having a high light intensity (a side lobe) at the periphery of the light transmitting portion of the phase shift mask of attenuation type.
摘要翻译：根据衰减类型的相移掩模及其制造方法，在光透射部分附近和周围的移相器部分的规定区域设置辅助图案，用于控制曝光光的一部分对应于该区域的暴露材料。辅助图案能够消除旁瓣的光强度，从而防止在衰减类型的相移掩模的光透射部分的周围产生具有高光强（侧瓣）的区域。

3. 发明授权

US5989756A Photo mask and method for fabricating semiconductor devices using the photo mask 失效
标题翻译：使用光掩模制造半导体器件的光掩模和方法
公开(公告)号：US5989756A
公开(公告)日：1999-11-23
申请号：US55261
申请日：1998-04-06
申请人： Akihiro Nakae
发明人： Akihiro Nakae
IPC分类号： G03F1/36 , G03F1/70 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F1/36 , G03F7/70058
摘要： A photoresist mask for use in a photolithographic process for fabricating semiconductor devices. The photo mask including a transparent substrate, and at least two light blocking regions. The at least two light blocking regions are separated by a first opening and arranged at a first pitch P.sub.1 satisfying the following relationship on a main surface of the transparent substrate in a first direction:P.sub.1 >2.lambda./NA (1+.sigma.)where .lambda. represents a wavelength of exposure light in an exposure system, NA represents a numerical aperture of the exposure system and C represents coherency of the exposure light. The at least two light blocking regions are formed with second openings at second pitches smaller than the first pitch in the first direction and the second openings have the exposure light transmitting therethrough, which has a weaker intensity than the exposure light transmitting through the first opening.
摘要翻译：用于制造半导体器件的光刻工艺中的光致抗蚀剂掩模。所述光掩模包括透明基板和至少两个遮光区域。所述至少两个遮光区域由第一开口分开，并且在第一方向上以透明基板的主表面满足以下关系的第一间距P1布置：P1>2λ/ NA（1+ sigma），其中λ 表示曝光系统中的曝光光的波长，NA表示曝光系统的数值孔径，C表示曝光光的相干性。所述至少两个遮光区域形成为具有比第一方向上的第一间距小的第二间距的第二开口，并且第二开口具有透射通过的曝光光，其强度比通过第一开口透射的曝光光强弱。

4. 发明申请

US20130084684A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20130084684A1
公开(公告)日：2013-04-04
申请号：US13612630
申请日：2012-09-12
申请人： Yasushi ISHII , Hiraku CHAKIHARA , Takahiro MARUYAMA , Akihiro NAKAE
发明人： Yasushi ISHII , Hiraku CHAKIHARA , Takahiro MARUYAMA , Akihiro NAKAE
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L27/11573 , H01L28/60 , H01L29/42344 , H01L29/66833 , H01L29/792 , H01L2223/54426 , H01L2223/5446
摘要： The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.
摘要翻译：本发明提高了具有分裂栅极结构的非易失性存储单元的半导体器件的生产成本。存储垫的端部被覆盖的下层抗蚀剂膜的电平差为绅士，改善了形成在下层抗蚀剂膜上的抗蚀剂中间层的厚度的均匀性，并且防止了局部厚度减小或消失通过在形成在半导体衬底的存储单元区域中的每个选择栅极上形成氧化硅膜和氮化硅膜之后，在位于最外侧的选择栅电极上去除氧化硅膜和氮化硅膜（虚拟单元区域）。

5. 发明授权

US06801297B2 Exposure condition determination system 失效
标题翻译：曝光条件确定系统
公开(公告)号：US06801297B2
公开(公告)日：2004-10-05
申请号：US10318002
申请日：2002-12-13
申请人： Akihiro Nakae
发明人： Akihiro Nakae
IPC分类号： G03B2742
CPC分类号： G03F7/70491 , G03B27/42 , G03F7/705
摘要： An exposure condition determination system and method, including a database configured to store a first information about a past exposure; and an exposure condition determination unit configured to determine an exposure condition suitable for a new mask which is newly made, based on said first information stored in said database and a second information about an exposure using said new mask. The first information includes at least one of a) a first mask information about properties of a mask used in said pas exposure; b) a first resist process information about properties of a resist process employed in said past exposure; c) an exposure condition information about an exposure condition employed in said past exposure; and d) a first aligner information about properties of an aligner.
摘要翻译：一种曝光条件确定系统和方法，包括被配置为存储关于过去曝光的第一信息的数据库; 以及曝光条件确定单元，被配置为基于存储在所述数据库中的所述第一信息和关于使用所述新掩码的曝光的第二信息来确定适合于新制作的新掩模的曝光条件。第一信息包括以下中的至少一个：a）关于在所述pas曝光中使用的掩模的属性的第一掩模信息; b）关于在所述过去曝光中使用的抗蚀剂工艺的性质的第一抗蚀剂工艺信息; c）关于在所述过去暴露中使用的暴露条件的曝光条件信息; 以及d）关于对准器的属性的第一对准器信息。

6. 发明授权

US5955227A Pattern determination method 失效
标题翻译：模式确定方法
公开(公告)号：US5955227A
公开(公告)日：1999-09-21
申请号：US89492
申请日：1998-06-02
申请人： Kouichirou Tsujita , Junjiro Sakai , Akihiro Nakae
发明人： Kouichirou Tsujita , Junjiro Sakai , Akihiro Nakae
IPC分类号： G03F7/26 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F7/705
摘要： A pattern determination method includes a step for setting an interconnection width and the like, a step for representing the mask pattern and aperture configuration in functions, steps for calculating amplitude distribution of exposure light, a step for calculating intensity distribution of exposure light at an image plane, steps for calculating maximum, minimum, and reference intensity of exposure light, a step for determining exposure margin and focus margin, a step for storing data of qualification/disqualification of optical image formation, and a step for providing a display of a table. A configuration including four openings is set for the aperture. Determination of whether an optical image of an interconnection pattern can be formed or not is facilitated by the table in setting the interconnection pattern of a semiconductor device.
摘要翻译：图案确定方法包括设置互连宽度等的步骤，用于表示功能中的掩模图案和孔径配置的步骤，用于计算曝光光的幅度分布的步骤，用于计算图像上的曝光光的强度分布的步骤平面，用于计算曝光光的最大，最小和参考强度的步骤，用于确定曝光余量和聚焦余量的步骤，存储光学图像形成的资格/取消资格数据的步骤，以及用于提供表格显示的步骤。为孔径设置包括四个开口的构造。通过设置半导体器件的互连图案的方便，能够确定是否可以形成布线图案的光学图像。

7. 发明授权

US06916749B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06916749B2
公开(公告)日：2005-07-12
申请号：US10384572
申请日：2003-03-11
申请人： Kouichirou Tsujita , Akihiro Nakae
发明人： Kouichirou Tsujita , Akihiro Nakae
IPC分类号： H01L21/28 , H01L21/027 , H01L21/3213 , H01L21/31
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A multilayer structure which provides for optimization of a configuration of a patterned photoresist is designed. A multilayer structure (20) includes polysilicon (10), a silicon oxide film (11) and an anti-reflective film (12) which are deposited sequentially in the order noted, and a photoresist (13) is provided on the anti-reflective film (12), so that light for exposure is incident on the multilayer structure (20) through the photoresist (13). First, as a step (i), a range of thickness of the silicon oxide film (11) is determined so as to allow an absolute value of a reflection coefficient of the light for exposure at an interface between the anti-reflective film (12) and the photoresist (13) to be equal to or smaller than a first value. Subsequently, as a step (ii), the range of thickness of the silicon oxide film (11) determined in the step (i) is delimited so as to allow an absolute value of a phase of the reflection coefficient to be equal to or larger than a second value.
摘要翻译：设计了提供图案化光致抗蚀剂的配置优化的多层结构。多层结构（20）包括按顺序依次沉积的多晶硅（10），氧化硅膜（11）和抗反射膜（12），并且抗反射膜使得用于曝光的光通过光致抗蚀剂（13）入射到多层结构（20）上。首先，作为步骤（i），确定氧化硅膜（11）的厚度范围，以便允许抗反射膜（12）之间的界面处的曝光用光的反射系数的绝对值）和光致抗蚀剂（13）等于或小于第一值。随后，作为步骤（ii），限定在步骤（i）中确定的氧化硅膜（11）的厚度范围，以使反射系数的相位的绝对值等于或大于比第二个值。

8. 发明授权

US06760892B2 Apparatus for evaluating lithography process margin simulating layout pattern of semiconductor device 有权
标题翻译：用于评估半导体器件的光刻工艺裕度模拟布局图案的设备
公开(公告)号：US06760892B2
公开(公告)日：2004-07-06
申请号：US10183394
申请日：2002-06-28
申请人： Hironobu Taoka , Akihiro Nakae
发明人： Hironobu Taoka , Akihiro Nakae
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F7/70433 , G03F7/705
摘要： A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.
摘要翻译：光刻处理容限评估装置内的布局图形生成单元使用分析条件和存储在布局图案模板保持单元中的信息来生成多个设计布局图案。此外，模拟条件生成单元使用分析条件和存储在模拟条件模板保持单元中的信息来生成多个模拟条件。模拟单元使用生成的条件生成多个实际布局模式。因此，光刻处理余量评估装置可以降低操作负担并提高精度。

9. 发明授权

US08951860B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08951860B2
公开(公告)日：2015-02-10
申请号：US13612630
申请日：2012-09-12
申请人： Yasushi Ishii , Hiraku Chakihara , Takahiro Maruyama , Akihiro Nakae
发明人： Yasushi Ishii , Hiraku Chakihara , Takahiro Maruyama , Akihiro Nakae
IPC分类号： H01L21/336 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/792 , H01L27/115 , H01L49/02
CPC分类号： H01L21/28282 , H01L27/11573 , H01L28/60 , H01L29/42344 , H01L29/66833 , H01L29/792 , H01L2223/54426 , H01L2223/5446
摘要： The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.
摘要翻译：本发明提高了具有分裂栅极结构的非易失性存储单元的半导体器件的生产成本。存储垫的端部被覆盖的下层抗蚀剂膜的电平差为绅士，改善了形成在下层抗蚀剂膜上的抗蚀剂中间层的厚度的均匀性，并且防止了局部厚度减小或消失通过在形成在半导体衬底的存储单元区域中的每个选择栅极上形成氧化硅膜和氮化硅膜之后，在位于最外侧的选择栅电极上去除氧化硅膜和氮化硅膜（虚拟单元区域）。

10. 发明授权

US5888677A Exposure mask, method of fabricating same, and method of manufacturing semiconductor device 失效
标题翻译：曝光掩模，其制造方法以及制造半导体器件的方法
公开(公告)号：US5888677A
公开(公告)日：1999-03-30
申请号：US882999
申请日：1997-06-26
申请人： Akihiro Nakae
发明人： Akihiro Nakae
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F7/70125 , G03F1/36 , G03F7/70433
摘要： An exposure mask has a predetermined principal pattern formed on a principal surface of a mask substrate and including a continuous pattern of lines which are repeatedly arranged at a first interval and an isolated pattern which is arranged adjacent to a line of the continuous pattern at a second interval greater than the first interval; and an auxiliary pattern formed along a direction in which the predetermined principal pattern is arranged, adapted to overcome multiple-beam-flux interference of diffracted light on a pupil's plane by providing the isolated pattern with cyclicity, and having a line width which falls outside a limit of resolution on a plane of projection of exposing light. Also disclosed are a method of fabricating the mask, and a method of manufacturing semiconductor devices using the mask.
摘要翻译：曝光掩模具有形成在掩模基板的主表面上的预定主图形，并且包括以第一间隔重复布置的连续图案，并且在第二间隔处布置成与连续图案的线相邻布置的隔离图案间隔大于第一个间隔; 以及沿着预定主图形排列的方向形成的辅助图案，其适于通过提供具有循环性的隔离图案来克服衍射光在瞳孔平面上的多光束通量干扰，并且具有落在曝光光投射平面上的分辨率极限。还公开了制造掩模的方法，以及使用该掩模制造半导体器件的方法。

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