专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08779523B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08779523B2
公开(公告)日：2014-07-15
申请号：US13491909
申请日：2012-06-08
申请人： Koji Shirai , Ken Inadumi , Tsuyoshi Hirayu , Toshihiro Sakamoto
发明人： Koji Shirai , Ken Inadumi , Tsuyoshi Hirayu , Toshihiro Sakamoto
IPC分类号： H01L29/76
CPC分类号： H01L27/092 , H01L21/823814 , H01L21/823892 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/42368 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate with a p-type conductivity, a buried layer with an n-type conductivity provided on the semiconductor substrate, a back gate layer with a p-type conductivity provided on the buried layer, a drain layer with an n-type conductivity provided on the back gate layer, a source layer with an n-type conductivity provided spaced from the drain layer, a gate electrode provided in a region immediately above a portion of the back gate layer between the drain layer and the source layer, and a drain electrode in contact with a part of an upper surface of the drain layer. A thickness of the drain layer in a region immediately below a contact surface between the drain layer and the drain electrode is half a total thickness of the back gate and drain layers in the region.
摘要翻译：根据一个实施例，半导体器件包括具有p型导电性的半导体衬底，设置在半导体衬底上的具有n型导电体的掩埋层，设置在掩埋层上的具有p型导电性的背栅层，设置在背栅层上的具有n型导电性的漏极层，与漏极层隔开设置的具有n型导电性的源极层，设置在背栅层之间的紧邻上部的区域之间的栅电极漏极层和源极层，以及与漏极层的上表面的一部分接触的漏电极。在漏极层和漏极之间的接触表面正下方的区域中的漏极层的厚度是该区域中的背栅极和漏极层的总厚度的一半。

2. 发明授权

US08304827B2 Semiconductor device having on a substrate a diode formed by making use of a DMOS structure 有权
标题翻译：在衬底上具有通过利用DMOS结构形成的二极管的半导体器件
公开(公告)号：US08304827B2
公开(公告)日：2012-11-06
申请号：US12644734
申请日：2009-12-22
申请人： Yuki Nakamura , Koji Shirai , Hirofumi Nagano , Jun Morioka , Tsubasa Yamada , Kazuaki Yamaura , Yasunori Iwatsu
发明人： Yuki Nakamura , Koji Shirai , Hirofumi Nagano , Jun Morioka , Tsubasa Yamada , Kazuaki Yamaura , Yasunori Iwatsu
IPC分类号： H01L29/66
CPC分类号： H01L27/0635 , H01L27/0629
摘要： A semiconductor device includes a diode formed by making use of a DMOS transistor structure. In addition to such a DMOS transistor structure, the semiconductor device includes a second buried layer of the first conductivity type being provided on a first buried layer of a second conductivity type that is in a floating state. Moreover, the second buried layer of the first conductivity type and a second diffusion region of the first conductive type are connected by a first diffusion region of the first conductivity type. A first electrode is set as anode, and a second electrode and a third electrode are short-circuited and set as cathode.
摘要翻译：半导体器件包括通过利用DMOS晶体管结构形成的二极管。除了这种DMOS晶体管结构之外，半导体器件包括第一导电类型的第二掩埋层，其设置在处于浮置状态的第二导电类型的第一掩埋层上。此外，第一导电类型的第二掩埋层和第一导电类型的第二扩散区域通过第一导电类型的第一扩散区域连接。第一电极被设置为阳极，第二电极和第三电极被短路并设置为阴极。

3. 发明申请

US20080140229A1 Method for optimizing an industrial product, system for optimizing an industrial product and method for manufacturing an industrial product 失效
标题翻译：优化工业产品的方法，优化工业产品的系统和制造工业产品的方法
公开(公告)号：US20080140229A1
公开(公告)日：2008-06-12
申请号：US12007723
申请日：2008-01-15
申请人： Kazumi Nishinohara , Mitsutoshi Nakamura , Kyoichi Suguro , Koji Shirai , Ichiro Taguchi
发明人： Kazumi Nishinohara , Mitsutoshi Nakamura , Kyoichi Suguro , Koji Shirai , Ichiro Taguchi
IPC分类号： G05B13/02
CPC分类号： G05B19/41885 , G05B2219/45031 , Y02P90/20 , Y02P90/26
摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.
摘要翻译：一种用于优化工业产品结构的方法包括从影响目标特性的制造参数中选择控制因子，该目标特性被安排由一系列制造过程制造; 设定各个控制因素的水平; 从结构的特征中选择具有与目标特性的权衡关系的参考特征; 将参考值设置为参考特性; 选择影响参考特征的先前调整因子; 创建将各级的组合分配给各个控制因素的实验条件; 确定现有调整因子的调整值，使得通过实验获得的参考特性的每个特征值基本上符合参考值; 以及使用所述调整值来确定所述目标特性的实验特性值。

4. 发明授权

US07027810B2 Method of determining electric field state of mobile station also in view of electric field state of uplink 失效
公开(公告)号：US07027810B2
公开(公告)日：2006-04-11
申请号：US10238635
申请日：2002-09-11
申请人： Koji Shirai
发明人： Koji Shirai
IPC分类号： H04Q7/20 , H04Q7/216 , H04B7/00 , H04B1/69
CPC分类号： H04B17/318 , H04B17/21 , H04W52/221
摘要： A method of determining the present electric field state of a mobile station also in view of an uplink electric field state is disclosed. A TPC bit counter is supplied with a received signal processed by a baseband processor, and counts TPC bits contained in one radio frame. An electric field state determining unit measures the electric field strength of the received signal from the base station which has been received by an RF receiver. A received electric field strength measuring unit determines a TPC bit evaluation value from the TPC bit sum calculated by TPC bit counter, determines a received electric field strength evaluation value from the received electric field strength measured by the electric field state determining unit, multiplies the TPC bit evaluation value by the received electric field strength evaluation value to calculates an electric field state evaluation value, and controls an alarm unit, a display unit, and an LED unit based on the calculated electric field state evaluation value for thereby indicating the electric field state.

5. 发明授权

US4884116A Double diffused mosfet with potential biases 失效
标题翻译：双重扩散的mosfet与潜在的偏见
公开(公告)号：US4884116A
公开(公告)日：1989-11-28
申请号：US132032
申请日：1987-12-14
申请人： Koji Shirai
发明人： Koji Shirai
IPC分类号： H01L21/322 , H01L21/336 , H01L21/762 , H01L27/06 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7824 , H01L21/3226 , H01L21/76251 , H01L27/0688 , H01L29/78612 , H01L29/78624 , H01L29/78654 , H01L2924/0002
摘要： First and second single crystal silicon substrates are integrated, by means of a thermal treatment, with first and second silicon oxide films formed on surfaces of said respective first and second single crystal silicon substrates in contact with eacth other. More specifically, an insulating region is formed by integrating first and second silicon oxide films formed on the first and second single crystal silicon substrates. First and second semiconductor regions constituted by the first and second single crystal silicon substrates are electrically isolated by the insulating region. As a result, it is possible to reduce the width of the depletion layer generated in the second semiconductor region by the influence of the first semiconductor region in which an element is formed. A back gate region formed in the second semiconductor region and the first semiconductor region, in which an element is not formed, are held substantially at an equal potential. In this way, it is possible to improve the yield voltage characteristics between the first semiconductor region, which does not form any element, and the back gate region. The insulating region which electrically isolates the first and second semiconductor regions from each other, is formed by bonding together first and second silicon oxide films on surface of the first and second single crystal silicon substrates. Therefore, the process of manufacture is simplified.
摘要翻译：通过热处理将第一和第二单晶硅衬底与形成在所述相应的第一和第二单晶硅衬底的表面上的第一和第二氧化硅膜彼此接触。更具体地，通过集成形成在第一和第二单晶硅衬底上的第一和第二氧化硅膜形成绝缘区域。由第一和第二单晶硅衬底构成的第一和第二半导体区域被绝缘区域电隔离。结果，可以通过形成元件的第一半导体区域的影响来减小在第二半导体区域中产生的耗尽层的宽度。形成在第二半导体区域中的背栅极区域和不形成元件的第一半导体区域基本保持相等的电位。以这种方式，可以提高不形成任何元件的第一半导体区域与后栅极区域之间的屈服电压特性。通过将第一和第二单晶硅基板的表面上的第一和第二氧化硅膜接合在一起，形成将第一和第二半导体区域彼此电隔离的绝缘区域。因此，简化了制造过程。

6. 发明授权

US4878096A Semiconductor device IC with DMOS using self-aligned back gate region 失效
标题翻译：具有DMOS的半导体器件IC采用自对准背栅区
公开(公告)号：US4878096A
公开(公告)日：1989-10-31
申请号：US27406
申请日：1987-03-18
申请人： Koji Shirai , Ken Kawamura
发明人： Koji Shirai , Ken Kawamura
IPC分类号： H01L21/336 , H01L21/761 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823462 , H01L21/761 , H01L21/823857 , H01L27/0922 , H01L27/088 , Y10S148/031 , Y10S148/082
摘要： In a semiconductor device according to the present invention, a pair of element regions of a second conductivity type are formed so as to be electrically isolated from each other on a semiconductor substrate of a first conductivity type, a complementary MOS transistor is formed in one of the element regions of the second conductivity type, and a double-diffused MOS transistor is formed in the other element region of the second conductivity type. The complementary MOS transistor is of a surface channel type in which N- and P-channel MOS transistors are respectively formed in a pair of well diffusion layers of the first and second conductivity types formed in the element region of the second conductivity type, and conductivity types of the respective gate electrodes of the N- and P-channel MOS transistors are different from those of the respective well diffusion layers. The double-diffused MOS transistor is of a surface channel type in which a back gate region is formed so as to be self-aligned with the gate electrode and the conductivity type of the gate electrode is different from that of the well diffusion layer.
摘要翻译：在根据本发明的半导体器件中，一对第二导电类型的元件区域形成为在第一导电类型的半导体衬底上彼此电隔离，互补MOS晶体管形成为第二导电类型的元件区域和双扩散MOS晶体管形成在第二导电类型的另一元件区域中。互补MOS晶体管是表面沟道型，其中N沟道MOS晶体管和P沟道MOS晶体管分别形成在形成在第二导电类型的元件区域中的第一和第二导电类型的一对阱扩散层中，并且导电性 N沟道MOS晶体管和P沟道MOS晶体管的各个栅极的类型与各个阱扩散层的不同。双扩散MOS晶体管是表面沟道型，其中形成背栅区以与栅电极自对准，并且栅电极的导电类型不同于阱扩散层的导电类型。

7. 发明申请

US20120139005A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120139005A1
公开(公告)日：2012-06-07
申请号：US13053123
申请日：2011-03-21
申请人： Takehito IKIMURA , Rieko Akimoto , Kiminori Watanabe , Koji Shirai , Yasushi Fukai
发明人： Takehito IKIMURA , Rieko Akimoto , Kiminori Watanabe , Koji Shirai , Yasushi Fukai
IPC分类号： H01L29/739
CPC分类号： H01L29/7322 , H01L27/0623 , H01L29/0653 , H01L29/0878 , H01L29/7816
摘要： According to one embodiment, a semiconductor device includes a p-type semiconductor layer, an n-type source region, an insulator, an n-type semiconductor region, an n-type drain region, a p-type channel region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and an electrode. The source region is provided on a surface of the p-type semiconductor layer. The insulator is provided in a trench formed extending in a thickness direction of the p-type semiconductor layer from the surface of the p-type semiconductor layer. The n-type semiconductor region is provided on the surface of the p-type semiconductor layer between the source region and the insulator. The drain region is provided on the surface of the p-type semiconductor layer between the source region and the n-type semiconductor region and separated from the source region and the n-type semiconductor region. The channel region is provided on the surface of the p-type semiconductor layer between the source region and the drain region and adjacent to the source region and the drain region. The gate insulating film is provided on the channel region. The gate electrode is provided on the gate insulating film. The source electrode is connected to the source region. The drain electrode is connected to the drain region. The electrode is connected to the n-type semiconductor region.
摘要翻译：根据一个实施例，半导体器件包括p型半导体层，n型源极区，绝缘体，n型半导体区，n型漏极区，p型沟道区，栅极绝缘膜，栅电极，源电极，漏电极和电极。源区域设置在p型半导体层的表面上。绝缘体设置在从p型半导体层的表面沿着p型半导体层的厚度方向延伸的沟槽中。 n型半导体区域设置在源极区域和绝缘体之间的p型半导体层的表面上。漏极区域设置在源极区域和n型半导体区域之间的p型半导体层的表面上，并与源极区域和n型半导体区域分离。沟道区域设置在源极区域和漏极区域之间并且与源极区域和漏极区域相邻的p型半导体层的表面上。栅极绝缘膜设置在沟道区域上。栅电极设置在栅极绝缘膜上。源电极连接到源极区域。漏电极连接到漏区。电极连接到n型半导体区域。

8. 发明申请

US20050017301A1 Semiconductor device having a diffusion layer and a manufacturing method thereof 审中-公开
标题翻译：具有扩散层的半导体器件及其制造方法
公开(公告)号：US20050017301A1
公开(公告)日：2005-01-27
申请号：US10793925
申请日：2004-03-08
申请人： Yasunori Iwatsu , Koji Shirai , Yuri Tamura
发明人： Yasunori Iwatsu , Koji Shirai , Yuri Tamura
IPC分类号： H01L21/761 , H01L21/336 , H01L21/74 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66568 , H01L21/74 , H01L29/1083 , H01L29/66659 , H01L29/7833 , H01L29/7835
摘要： A semiconductor device having a diffusion layer comprising: a semiconductor substrate of a first conductivity type comprising first and second portions having first and second impurity density, respectively, the first portion located so as to surround the second portion; a transistor having a first diffusion layer and a gate electrode, the first diffusion layer of the transistor formed in the first portion of the semiconductor substrate and having a third impurity density; and a semiconductor well of a second conductivity type formed between the first portion and the second portion of the semiconductor substrate, the semiconductor well having a fourth impurity density and formed so as to surround the first portion of the semiconductor substrate and located in the second portion of the semiconductor substrate.
摘要翻译：一种具有扩散层的半导体器件，包括：第一导电类型的半导体衬底，分别包括具有第一和第二杂质浓度的第一和第二部分，所述第一部分被定位成围绕第二部分; 具有第一扩散层和栅电极的晶体管，所述晶体管的所述第一扩散层形成在所述半导体衬底的第一部分中并具有第三杂质浓度; 以及形成在所述半导体衬底的所述第一部分和所述第二部分之间的第二导电类型的半导体阱，所述半导体阱具有第四杂质浓度并且被形成为围绕所述半导体衬底的所述第一部分并且位于所述第二部分中的半导体衬底。

9. 发明授权

US5087954A MOS-type integrated circuit 失效
标题翻译： MOS型集成电路
公开(公告)号：US5087954A
公开(公告)日：1992-02-11
申请号：US598206
申请日：1990-10-16
申请人： Koji Shirai
发明人： Koji Shirai
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L29/78
CPC分类号： H01L27/092
摘要： In a MOS-type integrated circuit, a source and a gate of a double diffusion MOSFET of an n-channel type and a drain and a gate of a double diffusion MOSFET of a p-channel type are in an island region surrounded by an n-type annular contact region having high impurity concentration. An n epitaxial layer, in each island region, is used for the sources and drains of both MOSFETs. The drain electrode of the p-channel MOSFET is connected to the gate electrode of the n-channel MOSFET. With this structure, the power consumption of the circuit is decreased, and the operating speed thereof is increased.

10. 发明授权

US5075754A Semiconductor device having improved withstanding voltage characteristics 失效
标题翻译：具有改善的耐电压特性的半导体器件
公开(公告)号：US5075754A
公开(公告)日：1991-12-24
申请号：US622146
申请日：1990-12-04
申请人： Koji Shirai , Ken Kawamura
发明人： Koji Shirai , Ken Kawamura
IPC分类号： H01L29/06 , H01L29/40
CPC分类号： H01L29/404
摘要： A semiconductor device comprises a substrate including a p-type first semiconductor region, an n-type second semiconductor region formed in the first semiconductor region, a first insulating layer formed on surfaces of the first semiconductor region and the second semiconductor region, a first conductive layer formed, via the first insulating layer, over the surface of the second semiconductor region, and set at substantially the same potential as that of the second semiconductor region, an n-type third semiconductor region formed to be spaced apart from the second semiconductor region and formed in the first semiconductor region so that a part of the third semiconductor region overlaps a part of the first conductive layer, via the first insulating layer, a second conductive layer connected to the third semiconductor region through an opening formed in the first insulating layer, and a wiring layer formed on a second insulating layer provided on surfaces of the first and second conductive layers.
摘要翻译：半导体器件包括：衬底，其包括p型第一半导体区域，形成在第一半导体区域中的n型第二半导体区域，形成在第一半导体区域和第二半导体区域的表面上的第一绝缘层，第一导电通过第一绝缘层在第二半导体区域的表面上形成并且设置为与第二半导体区域的电位基本相同的电位，形成为与第二半导体区域间隔开的n型第三半导体区域并且形成在第一半导体区域中，使得第三半导体区域的一部分经由第一绝缘层与第一导电层的一部分重叠，通过形成在第一绝缘层中的开口连接到第三半导体区域的第二导电层以及形成在设置在第一和第二导体的表面上的第二绝缘层上的布线层 ive层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式