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    • 1. 发明申请
      US20120139005A1 SEMICONDUCTOR DEVICE 审中-公开
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120139005A1
    • 2012-06-07
    • US13053123
    • 2011-03-21
    • Takehito IKIMURA , Rieko Akimoto , Kiminori Watanabe , Koji Shirai , Yasushi Fukai
    • Takehito IKIMURA , Rieko Akimoto , Kiminori Watanabe , Koji Shirai , Yasushi Fukai
    • H01L29/739
    • H01L29/7322 , H01L27/0623 , H01L29/0653 , H01L29/0878 , H01L29/7816
    • According to one embodiment, a semiconductor device includes a p-type semiconductor layer, an n-type source region, an insulator, an n-type semiconductor region, an n-type drain region, a p-type channel region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and an electrode. The source region is provided on a surface of the p-type semiconductor layer. The insulator is provided in a trench formed extending in a thickness direction of the p-type semiconductor layer from the surface of the p-type semiconductor layer. The n-type semiconductor region is provided on the surface of the p-type semiconductor layer between the source region and the insulator. The drain region is provided on the surface of the p-type semiconductor layer between the source region and the n-type semiconductor region and separated from the source region and the n-type semiconductor region. The channel region is provided on the surface of the p-type semiconductor layer between the source region and the drain region and adjacent to the source region and the drain region. The gate insulating film is provided on the channel region. The gate electrode is provided on the gate insulating film. The source electrode is connected to the source region. The drain electrode is connected to the drain region. The electrode is connected to the n-type semiconductor region.
    • 根据一个实施例，半导体器件包括p型半导体层，n型源极区，绝缘体，n型半导体区，n型漏极区，p型沟道区，栅极绝缘 膜，栅电极，源电极，漏电极和电极。 源区域设置在p型半导体层的表面上。 绝缘体设置在从p型半导体层的表面沿着p型半导体层的厚度方向延伸的沟槽中。 n型半导体区域设置在源极区域和绝缘体之间的p型半导体层的表面上。 漏极区域设置在源极区域和n型半导体区域之间的p型半导体层的表面上，并与源极区域和n型半导体区域分离。 沟道区域设置在源极区域和漏极区域之间并且与源极区域和漏极区域相邻的p型半导体层的表面上。 栅极绝缘膜设置在沟道区域上。 栅电极设置在栅极绝缘膜上。 源电极连接到源极区域。 漏电极连接到漏区。 电极连接到n型半导体区域。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US4980743A Conductivity-modulation metal oxide semiconductor field effect transistor 失效
    • Conductivity-modulation metal oxide semiconductor field effect transistor
    • 电导率调制金属氧化物半导体场效应晶体管
    • US4980743A
    • 1990-12-25
    • US160277
    • 1988-02-25
    • Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
    • Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
    • H01L29/78 , H01L27/04 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/68 , H01L29/739 , H01L29/745
    • H01L29/405 , H01L29/0696 , H01L29/0834 , H01L29/402 , H01L29/7393 , H01L29/7395 , H01L29/7396 , H01L29/7455
    • A conductivity-modulation MOSFET employs a substrate of an N type conductivity as its N base. A first source layer of a heavily-doped N type conductivity is formed in a P base layer formed in the N base. A source electrode electrically conducts the P base and the source. A first gate electrode insulatively covers a channel region defined by the N.sup.+ source layer in the P base. A P drain layer is formed on an opposite substrate surface. An N.sup.+ second source layer is formed in a P type drain layer by diffusion to define a second channel region. A second gate electrode insulatively covers the second channel region, thus providing a voltage-controlled turn-off controlling transistor. A drain electrode of the MOSFET conducts the P type drain and second source. When the turn-off controlling transistor is rendered conductive to turn off the MOSFET a "shorted anode structure" is temporarily formed wherein the N type base is short-circuited to the drain electrode, whereby case, the flow of carriers accumulated in the N type base into the drain electrode is facilitated to accelerate dispersion of carriers upon turn-off of the transistors.
    • 导电调制型MOSFET采用N型导电性基板作为N基极。 在形成在N基底中的P基底层中形成重掺杂N型导电性的第一源极层。 源极电极导电P基极和源极。 第一栅极绝缘地覆盖由P基底中的N +源层限定的沟道区域。 在相对的基板表面上形成P漏极层。 通过扩散在P型漏极层中形成N +第二源极层，以限定第二沟道区。 第二栅电极绝缘地覆盖第二沟道区，从而提供电压控制关断控制晶体管。 MOSFET的漏电极导通P型漏极和第二源极。 当关断控制晶体管导通以关断MOSFET时，暂时形成“短路阳极结构”，其中N型基极短路到漏极，由此情况下，累积在N型的载流子 有助于在晶体管关断时加速载流子的散射。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US06707104B2 Lateral high-breakdown-voltage transistor 有权
    • Lateral high-breakdown-voltage transistor
    • 横向高击穿电压晶体管
    • US06707104B2
    • 2004-03-16
    • US10277744
    • 2002-10-23
    • Kiminori Watanabe , Keisuke Matsuoka , Takao Ito
    • Kiminori Watanabe , Keisuke Matsuoka , Takao Ito
    • H01L2978
    • H01L29/7816 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/7393 , H01L29/7801 , H01L29/7835
    • A lateral high-breakdown-voltage transistor comprises an n− drain region and an n+ source region formed in a p− silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p+ substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.
    • 横向高击穿电压晶体管包括彼此分离的在p型硅衬底中形成的n +漏极区域和n +源极区域，形成在与衬底绝缘的沟道上的栅极电极 ，形成在漏极区域中的n +漏极接触区域，经由漏极接触区域与漏极区域电连接的漏极布线，与源极区域形成的ap +衬底接触区域，以及与源极区域电连接的源极布线 并且还经由衬底接触区域连接到半导体层。 晶体管的特征在于，衬底接触区域具有与源极布线接触的相应部分，并且因此从源极布线的接触表面的内侧横向延伸到接触表面的外部。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5124773A Conductivity-modulation metal oxide semiconductor field effect transistor 失效
    • Conductivity-modulation metal oxide semiconductor field effect transistor
    • 电导率调制金属氧化物半导体场效应晶体管
    • US5124773A
    • 1992-06-23
    • US563720
    • 1990-08-07
    • Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
    • Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
    • H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739 , H01L29/745
    • H01L29/405 , H01L29/0696 , H01L29/0834 , H01L29/402 , H01L29/7393 , H01L29/7395 , H01L29/7396 , H01L29/7455
    • A conductivity-modulation MOSFET employs a substrate of an N type conductivity as its N base. A first source layer of a heavily-doped N type conductivity is formed in a P base layer formed in the N base. A source electrode electrically conducts the P base and the source. A first gate electrode insulatively covers a channel region defined by the N.sup.+ source layer in the P base. A P drain layer is formed on an opposite substrate surface. An N.sup.+ second source layer is formed in a P type drain layer by diffusion to define a second channel region. A second gate electrode insulatively covers the second channel region, thus providing a voltage-controlled turn-off controlling transistor. A drain electrode of the MOSFET conducts the P type drain and second source. When the turn-off controlling transistor is rendered conductive to turn off the MOSFET a "shorted anode structure" is temporarily formed wherein the N type base is short-circuited to the drain electrode, whereby case, the flow of carriers accumulated in the N type base into the drain electrode is facilitated to accelerate dispersion of carriers upon turn-off of the transistor.
    • 导电调制型MOSFET采用N型导电性基板作为N基极。 在形成在N基底中的P基底层中形成重掺杂N型导电性的第一源极层。 源极电极导电P基极和源极。 第一栅极绝缘地覆盖由P基底中的N +源层限定的沟道区域。 在相对的基板表面上形成P漏极层。 通过扩散在P型漏极层中形成N +第二源极层，以限定第二沟道区。 第二栅电极绝缘地覆盖第二沟道区，从而提供电压控制关断控制晶体管。 MOSFET的漏电极导通P型漏极和第二源极。 当关断控制晶体管导通以关断MOSFET时，暂时形成“短路阳极结构”，其中N型基极短路到漏极，由此情况下，累积在N型的载流子 有助于在晶体管截止时加速载流子的分散。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US5105243A Conductivity-modulation metal oxide field effect transistor with single gate structure 失效
    • Conductivity-modulation metal oxide field effect transistor with single gate structure
    • 具有单栅极结构的电导率调制金属氧化物场效应晶体管
    • US5105243A
    • 1992-04-14
    • US399342
    • 1989-08-25
    • Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
    • Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
    • H01L21/336 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739
    • H01L29/7396 , H01L29/0696 , H01L29/0834 , H01L29/402 , H01L29/405 , H01L29/7393 , H01L29/7395
    • There is disclosed a single-gate type conductivity-modulation field effect transistor having a first base layer, a second base layer, and a source layer formed in the second base layer. A source electrode is provided on a surface of the first base layer, for electrically shorting the second base layer with the source layer. A drain layer is provided in the first base layer surface. A drain electrode is formed on the layer surface to be in contact with the drain layer. A gate electrode is insulatively provided above the layer surface, for covering a certain surface portion of the second base layer which is positioned between the first base layer and the source layer to define a channel region below the gate electrode. A heavily-doped semiconductor layer is formed in the drain layer to have the opposite conductivity type to that of the drain layer. This semiconductor layer is in contact with the drain electrode. When the transistor is turned off, this layer facilitates carriers accumulated in the first base layer to flow into the drain electrode through the drain layer, thereby accelerating dispersion of the carriers in said transistor.
    • 公开了具有形成在第二基极层中的第一基极层，第二基极层和源极层的单栅极型导电调制场效应晶体管。 源极电极设置在第一基极层的表面上，用于使第二基极层与源极层电气短路。 在第一基层表面设置漏极层。 漏极电极形成在层表面上以与漏极层接触。 栅极电极被绝缘地设置在层表面之上，用于覆盖位于第一基极层和源极层之间的第二基极层的特定表面部分，以限定栅电极下方的沟道区。 在漏极层中形成重掺杂的半导体层，以具有与漏极层相反的导电类型。 该半导体层与漏电极接触。 当晶体管截止时，该层便于积聚在第一基极层中的载流子通过漏极层流入漏电极，从而加速载流子在所述晶体管中的分散。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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