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1. 发明授权

US5705081A Etching method 失效
标题翻译：蚀刻方法
公开(公告)号：US5705081A
公开(公告)日：1998-01-06
申请号：US531713
申请日：1995-09-21
申请人： Koichiro Inazawa , Shin Okamoto , Yoshifumi Tahara
发明人： Koichiro Inazawa , Shin Okamoto , Yoshifumi Tahara
IPC分类号： H05H1/46 , C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/311
CPC分类号： H01L21/31116 , H01L21/3065
摘要： An etching apparatus comprises a pair of electrodes provided to face each other in a processing vessel, a permanent magnet for forming a magnetic field substantially parallel to a surface of a to-be-processed object which is placed between the paired electrodes, a gas introduction section for introducing etching gas into the processing vessel, a high-frequency generator for applying high-frequency voltage to the paired electrodes for generating plasma, and a high-frequency control section for preventing plasma from being unevenly distributed by starting and stopping the application of high-frequency voltage by the high-frequency generator at fixed intervals.
摘要翻译：蚀刻装置包括在处理容器内设置成彼此相对的一对电极，用于形成基本上平行于被配置在一对电极之间的待处理物体的表面的磁场的永磁体，气体导入将用于将蚀刻气体引入处理容器的部分，将高频电压施加到用于产生等离子体的成对电极的高频发生器，以及用于通过启动和停止应用来防止等离子体不均匀分布的高频控制部分高频电压由高频发生器固定间隔。

2. 发明授权

US07326650B2 Method of etching dual damascene structure 有权
标题翻译：蚀刻双镶嵌结构的方法
公开(公告)号：US07326650B2
公开(公告)日：2008-02-05
申请号：US10399626
申请日：2001-10-01
申请人： Yoshihide Kihara , Shin Okamoto , Koichiro Inazawa , Tomoki Suemasa
发明人： Yoshihide Kihara , Shin Okamoto , Koichiro Inazawa , Tomoki Suemasa
IPC分类号： H01L21/302
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813
摘要： In an etching method for achieving a dual damascene structure by using at least one layer of a low-k film and at least one layer of a hard mask, a dummy film, which is ultimately not left in the dual damascene structure, is formed in at least one layer over the hard mask in order to prevent shoulder sag. By adopting this method, a dual damascene structure in which the extent of the shoulder sag at the hard mask is minimized can be achieved through etching.
摘要翻译：在通过使用至少一层低k膜和至少一层硬掩模层来实现双镶嵌结构的蚀刻方法中，最终不留在双镶嵌结构中的虚拟膜形成在至少一层在硬掩模上，以防止肩下垂。通过采用这种方法，可以通过蚀刻来实现在硬掩模处的肩部凹陷的程度最小化的双镶嵌结构。

3. 发明授权

US07119011B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07119011B2
公开(公告)日：2006-10-10
申请号：US10845581
申请日：2004-05-14
申请人： Akitoshi Harada , Shin Okamoto , Koichiro Inazawa
发明人： Akitoshi Harada , Shin Okamoto , Koichiro Inazawa
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76829 , H01L21/76835 , H01L2221/1026
摘要： This semiconductor device includes a substrate 60 to be processed, a first insulation film 64 arranged at a designated position on the substrate 60 to have a via-hole 71a, an organic film 65 formed on the first insulation film 64 and a second insulation film 66 formed on the organic film 65. Both of the organic film 65 and the second insulation film 66 have a trench 71b in communication with the via-hole 71a, in common. Additionally, a manufacturing method of this semiconductor device includes the processes of forming the organic film 65 on the substrate 60 to be processed, forming a film having a designated pattern on the organic film 65 while exposing a part of the organic film 65, and removing the exposed part of the organic film 65 from the substrate 60 to expose a foundation layer of the organic film 65.
摘要翻译：该半导体装置包括：被处理基板60，布置在基板60上的指定位置的具有通孔71a的第一绝缘膜64，形成在第一绝缘膜64上的有机膜65和第二绝缘膜 66形成在有机膜65上。有机膜65和第二绝缘膜66共同地具有与通孔71a连通的沟槽71b。此外，该半导体装置的制造方法包括在待加工的基板60上形成有机膜65的工序，在有机膜65的一部分露出的同时在有机膜65上形成具有指定图案的膜，从基板60露出部分有机膜65，露出有机膜65的基层。

4. 发明授权

US5595627A Plasma etching method 失效
标题翻译：等离子蚀刻法
公开(公告)号：US5595627A
公开(公告)日：1997-01-21
申请号：US597563
申请日：1996-02-02
申请人： Koichiro Inazawa , Shin Okamoto , Hisataka Hayashi , Takaya Matsushita
发明人： Koichiro Inazawa , Shin Okamoto , Hisataka Hayashi , Takaya Matsushita
IPC分类号： H05H1/46 , C23F4/00 , C30B33/12 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/00 , C09K13/00
CPC分类号： H01L21/31116
摘要： A plasma etching apparatus has a lower electrode for supporting a semiconductor wafer in a processing room, an upper electrode opposite to the lower electrode, and an RF power supply for applying an RF power across the upper and lower electrodes. An SiN layer as an underlayer having a shoulder portion, and an SiO.sub.2 layer covering the SiN layer are disposed on the wafer. A contact hole is formed in the SiO.sub.2 layer by etching so as to expose the shoulder portion of the SiN layer. A processing gas contains C.sub.4 F.sub.8 and CO. To set the etching selection ratio of SiO.sub.2 /SiN, the discharge duration of each part of the processing gas is used as a parameter. The progress of dissociation of C.sub.4 F.sub.8 is controlled by selecting the discharge duration. The discharge duration is determined by the residence time of each part of the processing gas and the application time of an RF power.
摘要翻译：等离子体蚀刻装置具有用于在处理室中支撑半导体晶片的下电极，与下电极相对的上电极，以及用于在上电极和下电极上施加RF电力的RF电源。作为具有肩部的底层的SiN层和覆盖SiN层的SiO 2层设置在晶片上。通过蚀刻在SiO 2层中形成接触孔，以露出SiN层的肩部。处理气体含有C4F8和CO。为了设定SiO 2 / SiN的蚀刻选择比，使用处理气体的各部分的排出持续时间作为参数。通过选择放电持续时间控制C4F8的离解进程。放电持续时间由处理气体的每个部分的停留时间和RF功率的施加时间决定。

5. 发明授权

US08048325B2 Method and apparatus for multilayer photoresist dry development 有权
标题翻译：多层光刻胶干式显影的方法和装置
公开(公告)号：US08048325B2
公开(公告)日：2011-11-01
申请号：US11970062
申请日：2008-01-07
申请人： Vaidyanathan Balasubramaniam , Koichiro Inazawa , Rie Inazawa , Rich Wise , Arpan Mahorawala , Siddhartha Panda
发明人： Vaidyanathan Balasubramaniam , Koichiro Inazawa , Rie Inazawa , Rich Wise , Arpan Mahorawala , Siddhartha Panda
IPC分类号： B44C1/22
CPC分类号： H01L21/67069 , H01L21/31138
摘要： A method for etching an organic anti-reflective coating (ARC) layer on a substrate in a plasma processing system comprising: introducing a process gas comprising ammonia (NH3), and a passivation gas; forming a plasma from the process gas; and exposing the substrate to the plasma. The process gas can, for example, constitute NH3 and a hydrocarbon gas such as at least one of C2H4, CH4, C2H2, C2H6, C3H4, C3H6, C3H8, C4H6, C4H8, C4H10, C5H8, C5H10, C6H6, C6H10, and C6H12. Additionally, the process chemistry can further comprise the addition of helium. The present invention further presents a method for forming a bilayer mask for etching a thin film on a substrate, wherein the method comprises: forming the thin film on the substrate; forming an ARC layer on the thin film; forming a photoresist pattern on the ARC layer; and transferring the photoresist pattern to the ARC layer with an etch process using a process gas comprising ammonia (NH3), and a passivation gas.
摘要翻译：一种在等离子体处理系统中蚀刻衬底上的有机抗反射涂层（ARC）层的方法，包括：引入包含氨（NH 3）和钝化气体的工艺气体; 从工艺气体形成等离子体; 并将衬底暴露于等离子体。处理气体可以例如构成NH 3和烃气体，例如C 2 H 4，CH 4，C 2 H 2，C 2 H 6，C 3 H 4，C 3 H 6，C 3 H 8，C 4 H 6，C 4 H 8，C 4 H 10，C 5 H 8，C 5 H 10，C 6 H 6，C 6 H 10和C 6 H 12中的至少一种。另外，工艺化学可以进一步包括添加氦。本发明还提供一种用于形成用于在衬底上蚀刻薄膜的双层掩模的方法，其中所述方法包括：在所述衬底上形成所述薄膜; 在薄膜上形成ARC层; 在ARC层上形成光刻胶图案; 以及使用包含氨（NH 3）和钝化气体的工艺气体的蚀刻工艺将光致抗蚀剂图案转移到ARC层。

6. 发明申请

US20100024983A1 PLASMA ETCHING UNIT 有权
标题翻译：等离子体蚀刻单元
公开(公告)号：US20100024983A1
公开(公告)日：2010-02-04
申请号：US12578007
申请日：2009-10-13
申请人： Masanobu Honda , Kazuya Nagaseki , Koichiro Inazawa , Shoichiro Matsuyama , Hisataka Hayashi
发明人： Masanobu Honda , Kazuya Nagaseki , Koichiro Inazawa , Shoichiro Matsuyama , Hisataka Hayashi
IPC分类号： H01L21/3065
CPC分类号： H01J37/32082 , H01J37/3266 , H01L21/31138 , H01L21/31144 , H01L21/76802
摘要： The present invention is a plasma etching method including: an arranging step of arranging a pair of electrodes oppositely in a chamber and making one of the electrodes support a substrate to be processed in such a manner that the substrate is arranged between the electrodes, the substrate having an organic-material film and an inorganic-material film; and an etching step of applying a high-frequency electric power to at least one of the electrodes to form a high-frequency electric field between the pair of the electrodes, supplying a process gas into the chamber to form a plasma of the process gas by means of the electric field, and selectively plasma-etching the organic-material film of the substrate with respect to the inorganic-material film by means of the plasma; wherein a frequency of the high-frequency electric power applied to the at least one of the electrodes is 50 to 150 MHz in the etching step.
摘要翻译：本发明是一种等离子体蚀刻方法，包括：将一对电极相对设置在室中并使其中一个电极以使基板布置在电极之间的方式支撑待加工基板的布置步骤，基板具有有机材料膜和无机材料膜; 以及蚀刻步骤，向所述电极中的至少一个施加高频电力，以在所述一对电极之间形成高频电场，将处理气体供应到所述室中以形成所述处理气体的等离子体，以通过电场的手段，通过等离子体选择性地等离子体蚀刻衬底相对于无机材料膜的有机材料膜; 其中在所述蚀刻步骤中施加到所述至少一个所述电极的所述高频电力的频率为50〜150MHz。

7. 发明授权

US06986851B2 Dry developing method 失效
标题翻译：干发展方法
公开(公告)号：US06986851B2
公开(公告)日：2006-01-17
申请号：US10486828
申请日：2002-08-13
申请人： Akinori Kitamura , Vaidya Nathan Balasubramaniam , Koichiro Inazawa , Masaru Nishino
发明人： Akinori Kitamura , Vaidya Nathan Balasubramaniam , Koichiro Inazawa , Masaru Nishino
IPC分类号： B44C1/22 , C03C15/00
CPC分类号： G03F7/265 , G03F7/0035 , G03F7/0757 , G03F7/094 , G03F7/36 , G03F7/405 , H01L21/31144
摘要： A dry developing method for drawing a resist formed on a processed body by leading processing gas between parallel flat electrodes installed in a vacuum processing container and forming the plasma of the processing gas by applying a high frequency power to the electrodes, comprising the step of plasma-processing the resist on an etched layer having an already developed upper layer resist containing silicon and a lower layer resist installed in contact with the lower layer of the upper layer resist, wherein the lower layer resist is processed by a first process for plasma-processing by using the mixed gas of carbon monoxide gas and oxygen gas and a second step for plasma-processing by using the mixed gas of nitrogen gas and hydrogen gas, whereby an accurate drawing can be applied efficiently to the resist.
摘要翻译：一种干式显影方法，用于通过在安装在真空处理容器中的平行平面电极之间引导处理气体并且通过向电极施加高频电力来形成处理气体的等离子体来形成加工体上形成的抗蚀剂，其包括等离子体在具有已经显影的上层抗蚀剂的蚀刻层上加工抗蚀剂，所述蚀刻层含有硅和与上层抗蚀剂的下层接触的下层抗蚀剂，其中下层抗蚀剂通过等离子体处理的第一工艺通过使用一氧化碳气体和氧气的混合气体，并且通过使用氮气和氢气的混合气体进行等离子体处理的第二步骤，由此可以有效地将抗蚀剂应用于抗蚀剂。

8. 发明授权

US08840753B2 Plasma etching unit 有权
标题翻译：等离子体蚀刻单元
公开(公告)号：US08840753B2
公开(公告)日：2014-09-23
申请号：US12578007
申请日：2009-10-13
申请人： Masanobu Honda , Kazuya Nagaseki , Koichiro Inazawa , Shoichiro Matsuyama , Hisataka Hayashi
发明人： Masanobu Honda , Kazuya Nagaseki , Koichiro Inazawa , Shoichiro Matsuyama , Hisataka Hayashi
IPC分类号： H01L21/306 , C23C16/50 , C23C16/00 , H01L21/311 , H01L21/768 , H01J37/32
CPC分类号： H01J37/32082 , H01J37/3266 , H01L21/31138 , H01L21/31144 , H01L21/76802
摘要： The present invention is a plasma etching method including: an arranging step of arranging a pair of electrodes oppositely in a chamber and making one of the electrodes support a substrate to be processed in such a manner that the substrate is arranged between the electrodes, the substrate having an organic-material film and an inorganic-material film; and an etching step of applying a high-frequency electric power to at least one of the electrodes to form a high-frequency electric field between the pair of the electrodes, supplying a process gas into the chamber to form a plasma of the process gas by means of the electric field, and selectively plasma-etching the organic-material film of the substrate with respect to the inorganic-material film by means of the plasma; wherein a frequency of the high-frequency electric power applied to the at least one of the electrodes is 50 to 150 MHz in the etching step.
摘要翻译：本发明是一种等离子体蚀刻方法，包括：将一对电极相对设置在室中并使其中一个电极以使基板布置在电极之间的方式支撑待加工基板的布置步骤，基板具有有机材料膜和无机材料膜; 以及蚀刻步骤，向所述电极中的至少一个施加高频电力，以在所述一对电极之间形成高频电场，将处理气体供应到所述室中以形成所述处理气体的等离子体，以通过电场的手段，通过等离子体选择性地等离子体蚀刻衬底相对于无机材料膜的有机材料膜; 其中在所述蚀刻步骤中施加到所述至少一个所述电极的所述高频电力的频率为50〜150MHz。

9. 发明授权

US07211197B2 Etching method and plasma processing method 有权
标题翻译：蚀刻方法和等离子体处理方法
公开(公告)号：US07211197B2
公开(公告)日：2007-05-01
申请号：US10902893
申请日：2004-08-02
申请人： Masaaki Hagihara , Koichiro Inazawa , Wakako Naito
发明人： Masaaki Hagihara , Koichiro Inazawa , Wakako Naito
IPC分类号： B44C1/22
CPC分类号： H01L21/31138 , H01L21/31116 , H01L21/32136 , H01L21/76802
摘要： A processing gas constituted of CH2F2, O2 and Ar is introduced into a processing chamber 102 of a plasma processing apparatus 100. The flow rate ratio of the constituents of the processing gas is set at CH2F2/O2/Ar=20 sccm/10 sccm/100 sccm. The pressure inside the processing chamber 102 is set at 50 mTorr. 500 W high frequency power with its frequency set at 13.56 MHz is applied to a lower electrode. 108 on which a wafer W is placed. The processing gas is raised to plasma and thus, an SiNx layer 206 formed on a Cu layer 204 is etched. The exposed Cu layer 204 is hardly oxidized and C and F are not injected into it.
摘要翻译：由等离子体处理装置100的处理室102引入由CH 2 2 2 O 2 O 2，O 2和Ar构成的处理气体。处理气体的成分的流量比设定为CH 2/2 / 2/2 / Ar = 20sccm / 10sccm / 100 sccm。处理室102内的压力设定在50mTorr。将其频率设定为13.56MHz的500W高频功率施加到下电极。 108，其上放置有晶片W. 处理气体升至等离子体，因此蚀刻在Cu层204上形成的SiN x层206。暴露的Cu层204几乎不被氧化，并且C和F不被注入其中。

10. 发明授权

US07125806B2 Etching method 有权
标题翻译：蚀刻方法
公开(公告)号：US07125806B2
公开(公告)日：2006-10-24
申请号：US10490107
申请日：2002-09-06
申请人： Akitoshi Harada , Koichiro Inazawa
发明人： Akitoshi Harada , Koichiro Inazawa
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/76813
摘要： An etching method comprises a step of forming a via hole structure based on a photoresist film layer (210) for forming a wiring pattern, a silicon oxide film layer (201) which is a hard mask layer formed under the photoresist film, and an organic Low-k film layer (203) formed under the hard mask layer, wherein in the step, the organic film layer and the organic Low-k film layer are etched by using a mixture gas of N2 gas, H2 gas, and a CF gas.
摘要翻译：蚀刻方法包括形成基于用于形成布线图案的光致抗蚀剂膜层（210）的通孔结构的步骤，作为在光致抗蚀剂膜下形成的硬掩模层的氧化硅膜层（201）和有机在硬掩模层下形成的低k膜层（203），其中在该步骤中，通过使用N 2气体的混合气体蚀刻有机膜层和有机Low-k膜层，H 2气体和CF气体。

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