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1. 发明授权

US06737700B1 Non-volatile memory cell structure and method for manufacturing thereof 有权
标题翻译：非易失性存储单元结构及其制造方法
公开(公告)号：US06737700B1
公开(公告)日：2004-05-18
申请号：US10249864
申请日：2003-05-13
申请人： Ko-Hsing Chang , Cheng-Yuan Hsu
发明人： Ko-Hsing Chang , Cheng-Yuan Hsu
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.
摘要翻译：公开了具有对称单元结构的非易失性存储单元。非易失性存储单元包括衬底，隧道氧化物层，两个浮动栅极，电介质层，多个间隔物，控制栅极和两个分离栅极。衬底具有至少两个源和位于源之间的漏极。浮动栅极形成在隧道氧化物层上，每个浮栅位于每个源极和漏极之间。电介质层形成在浮栅上。控制栅极形成在漏极之上并且在浮动栅极之间。分流门分别位于浮动门的外侧壁附近。因此，每个分离门通过每个浮动栅极与控制栅极相对。

2. 发明授权

US06794710B2 Split-gate flash memory structure and method of manufacture 有权
标题翻译：分流式闪存结构及其制造方法
公开(公告)号：US06794710B2
公开(公告)日：2004-09-21
申请号：US10064883
申请日：2002-08-27
申请人： Ko-Hsing Chang , Cheng-Yuan Hsu
发明人： Ko-Hsing Chang , Cheng-Yuan Hsu
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7883
摘要： A split-gate flash memory structure. The flash memory at least includes a substrate having a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench such that the upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate such that the select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.
摘要翻译：分闸式闪存结构。闪存至少包括其中具有沟槽的衬底，浮置栅极，选择栅极和源极/漏极区域。浮动栅极形成在沟槽内，使得浮动栅极的上表面在衬底表面下方。选择栅极也形成在浮置栅极上方的沟槽内，使得选择栅极突出超过衬底表面。源极/漏极区域形成在选择栅极的每一侧上的衬底中。源极/漏极区域和浮置栅极彼此间隔一定距离。隧道氧化层将浮置栅极与衬底分开，并且栅极电介质层将浮动栅极与选择栅极分离。电介质层将选择栅极与衬底分开。

3. 发明授权

US06867099B2 Spilt-gate flash memory structure and method of manufacture 有权
标题翻译：溢流闸闪存结构及制造方法
公开(公告)号：US06867099B2
公开(公告)日：2005-03-15
申请号：US10710784
申请日：2004-08-03
申请人： Ko-Hsing Chang , Cheng-Yuan Hsu
发明人： Ko-Hsing Chang , Cheng-Yuan Hsu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336
摘要： A split-gate flash memory structure. The flash memory at least includes a substrate having a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench such that the upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate such that the select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.
摘要翻译：分闸式闪存结构。闪存至少包括其中具有沟槽的衬底，浮置栅极，选择栅极和源极/漏极区域。浮动栅极形成在沟槽内，使得浮动栅极的上表面在衬底表面下方。选择栅极也形成在浮置栅极上方的沟槽内，使得选择栅极突出超过衬底表面。源极/漏极区域形成在选择栅极的每一侧上的衬底中。源极/漏极区域和浮置栅极彼此间隔一定距离。隧道氧化层将浮置栅极与衬底分开，并且栅极电介质层将浮动栅极与选择栅极分离。电介质层将选择栅极与衬底分开。

4. 发明授权

US06869842B2 Method for manufacturing non-volatile memory cell 有权
标题翻译：制造非易失性存储单元的方法
公开(公告)号：US06869842B2
公开(公告)日：2005-03-22
申请号：US10707418
申请日：2003-12-12
申请人： Ko-Hsing Chang , Cheng-Yuan Hsu
发明人： Ko-Hsing Chang , Cheng-Yuan Hsu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L21/336 , H01L21/331
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.
摘要翻译：公开了具有对称单元结构的非易失性存储单元。非易失性存储单元包括衬底，隧道氧化物层，两个浮动栅极，电介质层，多个间隔物，控制栅极和两个分离栅极。衬底具有至少两个源和位于源之间的漏极。浮动栅极形成在隧道氧化物层上，每个浮栅位于每个源极和漏极之间。电介质层形成在浮栅上。控制栅极形成在漏极之上并且在浮动栅极之间。分流门分别位于浮动门的外侧壁附近。因此，每个分离门通过每个浮动栅极与控制栅极相对。

5. 发明授权

US06635533B1 Method of fabricating flash memory 有权
标题翻译：制造闪存的方法
公开(公告)号：US06635533B1
公开(公告)日：2003-10-21
申请号：US10249256
申请日：2003-03-27
申请人： Ko-Hsing Chang , Cheng-Yuan Hsu
发明人： Ko-Hsing Chang , Cheng-Yuan Hsu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328
摘要： A method of fabricating a flash memory is provided. A pad layer and a mask layer are formed over the substrate, and then the mask layer is patterned for forming an opening therein. The pad layer exposed by the opening is removed. After a tunneling dielectric layer is formed on the bottom of the opening, a floating gate is formed on the sidewall of the opening. The top of the floating gate is lower than a surface of the mask layer. A source region is formed in the substrate. Thereafter, an inter-gate dielectric layer is formed in the opening and a control gate is filled in the opening. The mask layer is removed and then a gate dielectric layer is formed on the substrate and a spacer is formed on the sidewall of the floating gate and the control gate. A select gate is formed on the sidewall of the spacer. A drain region is formed in the substrate on one side of the select gate.
摘要翻译：提供一种制造闪速存储器的方法。在衬底上形成焊盘层和掩模层，然后对掩模层进行图案化以在其中形成开口。去除由开口暴露的垫层。在开口底部形成隧道电介质层之后，在开口的侧壁上形成浮栅。浮动栅极的顶部低于掩模层的表面。源极区域形成在衬底中。此后，在开口中形成栅极间电介质层，并且在开口中填充控制栅。去除掩模层，然后在衬底上形成栅极电介质层，并且在浮动栅极和控制栅极的侧壁上形成间隔物。选择栅极形成在间隔件的侧壁上。漏极区域形成在选择栅极一侧的衬底中。

6. 发明授权

US08890230B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08890230B2
公开(公告)日：2014-11-18
申请号：US13549510
申请日：2012-07-15
申请人： Cheng-Yuan Hsu , Chi Ren , Tzeng-Fei Wen
发明人： Cheng-Yuan Hsu , Chi Ren , Tzeng-Fei Wen
IPC分类号： H01L21/02
CPC分类号： H01L29/66825 , H01L21/266 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/42332 , H01L29/6653 , H01L29/6656 , H01L29/7881 , H01L29/7882
摘要： A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness.
摘要翻译：半导体器件包括两个浮置栅极，控制栅极和第一介电层。浮置栅极设置在半导体衬底上。控制栅极部分地重叠每个浮置栅极，并且控制栅极的一部分设置在两个浮置栅极之间。此外，设置在两个浮动栅极和控制栅极之间的第一介电层具有固定的厚度。

7. 发明授权

US07391073B2 Non-volatile memory structure and method of fabricating non-volatile memory 有权
标题翻译：非易失性存储器结构和制造非易失性存储器的方法
公开(公告)号：US07391073B2
公开(公告)日：2008-06-24
申请号：US11162497
申请日：2005-09-13
申请人： Tsung-Lung Chen , Hui-Hung Kuo , Cheng-Yuan Hsu , Chih-Wei Hung
发明人： Tsung-Lung Chen , Hui-Hung Kuo , Cheng-Yuan Hsu , Chih-Wei Hung
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.
摘要翻译：描述了制造非易失性存储器的方法。提供了在其上具有隧道层和浮栅的衬底。在浮动栅极上形成掩模层。掩模层具有露出浮栅的一部分的开口。然后，从开口去除浮栅的一部分，以在浮栅层的表面上形成凹陷区域。栅极间介电层形成在浮栅层上。在栅极间电介质层上形成控制栅极层。之后，去除掩模层和掩模层下的浮栅层以形成另一个开口。在开口内形成选择栅极层。

8. 发明申请

US20070128799A1 METHOD OF FABRICATING FLASH MEMORY 审中-公开
标题翻译：制作闪速存储器的方法
公开(公告)号：US20070128799A1
公开(公告)日：2007-06-07
申请号：US11669163
申请日：2007-01-31
申请人： Jui-Yu Pan , Cheng-Yuan Hsu , I-Chun Chuang , Chih-Wei Hung
发明人： Jui-Yu Pan , Cheng-Yuan Hsu , I-Chun Chuang , Chih-Wei Hung
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7782
摘要： A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The conductive spacers are patterned to form a plurality of floating gates. A plurality of buried doped regions is formed in the substrate under the bottom surface of the openings. An inter-gate dielectric layer is formed over the substrate. A plurality of control gates is formed over the substrate to fill the openings. The mask layer is removed to form a plurality of memory units. A plurality of source regions and drain regions are formed in the substrate beside the memory units.
摘要翻译：描述了一种用于制造闪速存储器的方法。在基板上形成具有露出基板的一部分的开口的掩模层。在开口的底表面处形成隧道电介质层。导电间隔件形成在开口的侧壁上。将导电间隔物图案化以形成多个浮动栅极。在开口底面下方的基板中形成多个掩埋掺杂区域。栅极间电介质层形成在衬底上。多个控制栅极形成在衬底上以填充开口。去除掩模层以形成多个存储单元。在存储单元旁边的基板中形成多个源极区域和漏极区域。

9. 发明申请

US20060205154A1 MANUFACTURING METHOD OF AN NON-VOLATILE MEMORY STRUCTURE 审中-公开
标题翻译：非易失性存储器结构的制造方法
公开(公告)号：US20060205154A1
公开(公告)日：2006-09-14
申请号：US11308796
申请日：2006-05-05
申请人： Chih-Wei Hung , Cheng-Yuan Hsu
发明人： Chih-Wei Hung , Cheng-Yuan Hsu
IPC分类号： H01L21/336
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/42344 , H01L29/792
摘要： A non-volatile memory including a substrate, a plurality of gate structures, a plurality of select gate structures, spacers and source region/drain region is provided. Each gate structure on the substrate further includes a bottom dielectric layer, an electron trapping layer, an upper dielectric layer, a control gate and a cap layer. The select gate structures are disposed on one side of the respective each gate structure. Each select gate structure includes a select gate dielectric layer and a select gate. The select gate structures and the gate structures are connected in series to form a memory cell row. The spacers are disposed between the select gate structures and the gate structures. The source region and the drain region are disposed in the substrate on each side of the memory cell row.
摘要翻译：提供了包括基板，多个栅极结构，多个选择栅极结构，间隔物和源极区域/漏极区域的非易失性存储器。基板上的每个栅极结构还包括底部电介质层，电子俘获层，上介电层，控制栅极和盖层。选择栅极结构设置在各个栅极结构的一侧。每个选择栅极结构包括选择栅极电介质层和选择栅极。选择栅极结构和栅极结构串联连接以形成存储单元行。间隔件设置在选择栅极结构和栅极结构之间。源极区域和漏极区域设置在存储单元行的每一侧的衬底中。

10. 发明授权

US06963105B2 Flash memory cell structure 失效
标题翻译：闪存单元结构
公开(公告)号：US06963105B2
公开(公告)日：2005-11-08
申请号：US10605419
申请日：2003-09-30
申请人： Chih-Wei Hung , Da Sung , Cheng-Yuan Hsu
发明人： Chih-Wei Hung , Da Sung , Cheng-Yuan Hsu
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L29/42328 , H01L29/7885
摘要： A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.
摘要翻译：闪存单元结构具有衬底，选择栅极，第一掺杂区域，浅第二掺杂区域，深第二掺杂区域和掺杂源极区域。衬底具有堆叠栅极。选择栅极形成在衬底上并且与堆叠栅极相邻。第一离子形成区域在衬底中被掺杂并且与选择栅极相邻，作为漏极。浅二次掺杂区形成在堆叠栅极下方的第一型掺杂区的一侧。用作阱的深二次掺杂区形成在第一型掺杂区的下方，其中一侧与浅二次掺杂区接壤。掺杂源区形成在浅二次掺杂区的一侧作为源。

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