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1. 发明授权

US07391073B2 Non-volatile memory structure and method of fabricating non-volatile memory 有权
标题翻译：非易失性存储器结构和制造非易失性存储器的方法
公开(公告)号：US07391073B2
公开(公告)日：2008-06-24
申请号：US11162497
申请日：2005-09-13
申请人： Tsung-Lung Chen , Hui-Hung Kuo , Cheng-Yuan Hsu , Chih-Wei Hung
发明人： Tsung-Lung Chen , Hui-Hung Kuo , Cheng-Yuan Hsu , Chih-Wei Hung
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.
摘要翻译：描述了制造非易失性存储器的方法。提供了在其上具有隧道层和浮栅的衬底。在浮动栅极上形成掩模层。掩模层具有露出浮栅的一部分的开口。然后，从开口去除浮栅的一部分，以在浮栅层的表面上形成凹陷区域。栅极间介电层形成在浮栅层上。在栅极间电介质层上形成控制栅极层。之后，去除掩模层和掩模层下的浮栅层以形成另一个开口。在开口内形成选择栅极层。

2. 发明申请

US20070128799A1 METHOD OF FABRICATING FLASH MEMORY 审中-公开
标题翻译：制作闪速存储器的方法
公开(公告)号：US20070128799A1
公开(公告)日：2007-06-07
申请号：US11669163
申请日：2007-01-31
申请人： Jui-Yu Pan , Cheng-Yuan Hsu , I-Chun Chuang , Chih-Wei Hung
发明人： Jui-Yu Pan , Cheng-Yuan Hsu , I-Chun Chuang , Chih-Wei Hung
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7782
摘要： A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The conductive spacers are patterned to form a plurality of floating gates. A plurality of buried doped regions is formed in the substrate under the bottom surface of the openings. An inter-gate dielectric layer is formed over the substrate. A plurality of control gates is formed over the substrate to fill the openings. The mask layer is removed to form a plurality of memory units. A plurality of source regions and drain regions are formed in the substrate beside the memory units.
摘要翻译：描述了一种用于制造闪速存储器的方法。在基板上形成具有露出基板的一部分的开口的掩模层。在开口的底表面处形成隧道电介质层。导电间隔件形成在开口的侧壁上。将导电间隔物图案化以形成多个浮动栅极。在开口底面下方的基板中形成多个掩埋掺杂区域。栅极间电介质层形成在衬底上。多个控制栅极形成在衬底上以填充开口。去除掩模层以形成多个存储单元。在存储单元旁边的基板中形成多个源极区域和漏极区域。

3. 发明申请

US20060205154A1 MANUFACTURING METHOD OF AN NON-VOLATILE MEMORY STRUCTURE 审中-公开
标题翻译：非易失性存储器结构的制造方法
公开(公告)号：US20060205154A1
公开(公告)日：2006-09-14
申请号：US11308796
申请日：2006-05-05
申请人： Chih-Wei Hung , Cheng-Yuan Hsu
发明人： Chih-Wei Hung , Cheng-Yuan Hsu
IPC分类号： H01L21/336
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/42344 , H01L29/792
摘要： A non-volatile memory including a substrate, a plurality of gate structures, a plurality of select gate structures, spacers and source region/drain region is provided. Each gate structure on the substrate further includes a bottom dielectric layer, an electron trapping layer, an upper dielectric layer, a control gate and a cap layer. The select gate structures are disposed on one side of the respective each gate structure. Each select gate structure includes a select gate dielectric layer and a select gate. The select gate structures and the gate structures are connected in series to form a memory cell row. The spacers are disposed between the select gate structures and the gate structures. The source region and the drain region are disposed in the substrate on each side of the memory cell row.
摘要翻译：提供了包括基板，多个栅极结构，多个选择栅极结构，间隔物和源极区域/漏极区域的非易失性存储器。基板上的每个栅极结构还包括底部电介质层，电子俘获层，上介电层，控制栅极和盖层。选择栅极结构设置在各个栅极结构的一侧。每个选择栅极结构包括选择栅极电介质层和选择栅极。选择栅极结构和栅极结构串联连接以形成存储单元行。间隔件设置在选择栅极结构和栅极结构之间。源极区域和漏极区域设置在存储单元行的每一侧的衬底中。

4. 发明授权

US06963105B2 Flash memory cell structure 失效
标题翻译：闪存单元结构
公开(公告)号：US06963105B2
公开(公告)日：2005-11-08
申请号：US10605419
申请日：2003-09-30
申请人： Chih-Wei Hung , Da Sung , Cheng-Yuan Hsu
发明人： Chih-Wei Hung , Da Sung , Cheng-Yuan Hsu
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L29/42328 , H01L29/7885
摘要： A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.
摘要翻译：闪存单元结构具有衬底，选择栅极，第一掺杂区域，浅第二掺杂区域，深第二掺杂区域和掺杂源极区域。衬底具有堆叠栅极。选择栅极形成在衬底上并且与堆叠栅极相邻。第一离子形成区域在衬底中被掺杂并且与选择栅极相邻，作为漏极。浅二次掺杂区形成在堆叠栅极下方的第一型掺杂区的一侧。用作阱的深二次掺杂区形成在第一型掺杂区的下方，其中一侧与浅二次掺杂区接壤。掺杂源区形成在浅二次掺杂区的一侧作为源。

5. 发明申请

US20070109851A1 METHOD OF MANUFACTURING NON-VOLATILE MEMORY AND METHOD OF OPERATING NON-VOLATILE MEMORY ARRAY 有权
标题翻译：制造非易失性存储器的方法和操作非易失性存储器阵列的方法
公开(公告)号：US20070109851A1
公开(公告)日：2007-05-17
申请号：US11621095
申请日：2007-01-08
申请人： Chih-Wei Hung , Cheng-Yuan Hsu , Da Sung
发明人： Chih-Wei Hung , Cheng-Yuan Hsu , Da Sung
IPC分类号： G11C16/04
CPC分类号： H01L21/28273 , G11C16/0433 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7923
摘要： A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.
摘要翻译：描述了制造非易失性存储器的方法。提供其上具有堆叠栅极结构的衬底。每个堆叠栅极结构包括选择栅极介电层，选择栅极和盖层。源极区和漏极区形成在衬底中。源极区域和漏极区域通过至少两个堆叠的栅极结构彼此分离。在衬底上形成隧穿电介质层，然后在隧道电介质层上形成第一导电层。图案化第一导电层以在堆叠栅极结构之间的间隙中形成浮栅。在衬底上形成栅极间电介质层之后，在衬底上形成第二导电层。图案化第二导电层以在相邻的堆叠栅极结构之间的间隙中形成相互连接的控制栅极。

6. 发明申请

US20060172491A1 NON-VOLATILE MEMORY STRUCTURE AND METHOD OF FABRICATING NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器结构和非易失性存储器的制作方法
公开(公告)号：US20060172491A1
公开(公告)日：2006-08-03
申请号：US11162497
申请日：2005-09-13
申请人： Tsung-Lung Chen , Hui-Hung Kuo , Cheng-Yuan Hsu , Chih-Wei Hung
发明人： Tsung-Lung Chen , Hui-Hung Kuo , Cheng-Yuan Hsu , Chih-Wei Hung
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.
摘要翻译：描述了制造非易失性存储器的方法。提供了在其上具有隧道层和浮栅的衬底。在浮动栅极上形成掩模层。掩模层具有露出浮栅的一部分的开口。然后，从开口去除浮栅的一部分，以在浮栅层的表面上形成凹陷区域。栅极间介电层形成在浮栅层上。在栅极间电介质层上形成控制栅极层。之后，去除掩模层和掩模层下的浮栅层以形成另一个开口。在开口内形成选择栅极层。

7. 发明授权

US07061805B2 P-channel NAND flash memory and operating method thereof 失效
标题翻译： P通道NAND闪存及其操作方法
公开(公告)号：US07061805B2
公开(公告)日：2006-06-13
申请号：US11160035
申请日：2005-06-06
申请人： Chih-Wei Hung , Cheng-Yuan Hsu
发明人： Chih-Wei Hung , Cheng-Yuan Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12
摘要： A p-channel NAND flash memory includes a plurality of memory cells in series connection between a p-type source region and a p-type drain region. Each memory cell includes a tunneling dielectric layer, a floating gate, and a control gate. An erase gate is formed between two adjacent memory cells, and a p-type doped region is formed in the substrate between two adjacent memory cells. A select transistor is formed between the p-type drain and the cell nearest to the p-type drain. The cells in the p-channel NAND flash memory is programmed by band-to-band tunneling induced hot carrier injection, and erased via F-N tunneling.
摘要翻译： p沟道NAND闪存包括在p型源极区域和p型漏极区域之间串联连接的多个存储单元。每个存储单元包括隧道介质层，浮动栅极和控制栅极。在两个相邻的存储单元之间形成擦除栅极，并且在两个相邻的存储单元之间的衬底中形成p型掺杂区域。在p型漏极和最靠近p型漏极的单元之间形成选择晶体管。 p通道NAND闪速存储器中的单元通过带 - 带隧道诱导的热载流子注入进行编程，并通过F-N隧穿进行擦除。

8. 发明授权

US07057940B2 Flash memory cell, flash memory cell array and manufacturing method thereof 失效
标题翻译：闪存单元，闪存单元阵列及其制造方法
公开(公告)号：US07057940B2
公开(公告)日：2006-06-06
申请号：US10907830
申请日：2005-04-18
申请人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
发明人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.
摘要翻译：闪存单元阵列包括衬底，一串存储器单元结构和源极区/漏极区。每个存储单元结构包括堆叠栅极结构，其包括在基板上形成的选择栅极介电层，选择栅极和栅极盖层; 间隔件设置在选择门的侧壁上; 连接到堆叠栅极结构的控制栅极设置在堆叠栅极结构的一侧; 在控制栅极和衬底之间设置浮置栅极; 在控制栅极和浮置栅极之间设置栅极间电介质层; 并且在浮置栅极和衬底之间设置隧道电介质层。源区域/漏极区域设置在闪存单元阵列的外部控制栅极和堆叠栅极结构附近的衬底中。

9. 发明申请

US20060040440A1 NAND FLASH MEMORY CELL ROW AND MANUFACTURING METHOD THEREOF 有权
标题翻译： NAND FLASH存储单元阵列及其制造方法
公开(公告)号：US20060040440A1
公开(公告)日：2006-02-23
申请号：US11163818
申请日：2005-10-31
申请人： Shih-Chang Chen , Cheng-Yuan Hsu , Chih-Wei Hung
发明人： Shih-Chang Chen , Cheng-Yuan Hsu , Chih-Wei Hung
IPC分类号： H01L21/8238
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/7881 , H01L29/7887
摘要： A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. Each of the second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and the adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is disposed between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are disposed under the first stacked gate structure, and the source/drain regions are in the exposed substrate.
摘要翻译： NAND闪存单元行包括第一和第二堆叠栅极结构，控制和浮置栅极，栅极间电介质层，隧道氧化物层，掺杂区域和源极/漏极区域。第一层叠栅极结构具有擦除栅极电介质层，擦除栅极和第一覆盖层。第二层叠栅极结构中的每一个具有选择栅极介电层，选择栅极和第二覆盖层。控制栅极位于每个第一层叠栅极结构之间，并且在第二层叠栅极结构中的每一个与相邻的第一层叠栅极结构之间。浮栅位于控制栅和基板之间。栅极间电介质层设置在控制栅极和浮栅之间。隧道氧化物位于浮栅和衬底之间。掺杂区域设置在第一层叠栅极结构之下，源极/漏极区域处于暴露的衬底中。

10. 发明申请

US20050253182A1 NON-VOLATILE MEMORY, NON-VOLATILE MEMORY ARRAY AND MANUFACTURING METHOD THEREOF 失效
标题翻译：非易失性存储器，非易失性存储器阵列及其制造方法
公开(公告)号：US20050253182A1
公开(公告)日：2005-11-17
申请号：US10904478
申请日：2004-11-12
申请人： Chih-Wei Hung , Cheng-Yuan Hsu , Da Sung
发明人： Chih-Wei Hung , Cheng-Yuan Hsu , Da Sung
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/792
CPC分类号： H01L21/28273 , G11C16/0433 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7923
摘要： A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stacked gate structures. The control gates are disposed over the substrate filling the space between the stacked gate structures and are mutually connected together. The floating gates are disposed between the stacked gate structures and positioned between the control gate and the substrate. The inter-gate dielectric layers are disposed between the control gates and the floating gates. The tunneling dielectric layers are disposed between the floating gates and the substrate. The source/drain regions are disposed in the substrate outside the two outermost stacked gate structures.
摘要翻译：提供非易失性存储器。在基板上形成多个堆叠的栅极结构。堆叠的栅极结构包括从衬底表面向上的选择栅极电介质层，选择栅极和覆盖层。间隔件设置在堆叠的栅极结构的侧壁上。控制栅极设置在填充层叠栅极结构之间的空间的衬底上，并且彼此连接在一起。浮置栅极位于堆叠的栅极结构之间并且位于控制栅极和衬底之间。栅极间电介质层设置在控制栅极和浮栅之间。隧道电介质层设置在浮置栅极和衬底之间。源极/漏极区域设置在两个最外层叠的栅极结构之外的衬底中。

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