专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070183549A1 Adaptive variable length pulse synchronizer 有权
标题翻译：自适应可变长度脉冲同步器
公开(公告)号：US20070183549A1
公开(公告)日：2007-08-09
申请号：US11349874
申请日：2006-02-08
申请人： John Angello , Satyavathi Akella , Kiyoshi Kase , May Len
发明人： John Angello , Satyavathi Akella , Kiyoshi Kase , May Len
IPC分类号： H04L25/38
CPC分类号： H04L25/38 , H04L7/0008
摘要： An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.
摘要翻译：一种自适应可变长度脉冲同步器，包括状态保持器电路，异步脉冲沿检测电路，数据同步电路和脉冲沿同步电路。状态保持电路检测异步脉冲的前沿。在状态保持电路检测到前沿之后，异步脉冲沿检测电路检测异步脉冲的后沿。在检测到异步脉冲之后，异步脉冲沿检测电路还提供与时钟信号同步的脉冲。数据同步电路锁存异步数据，并响应于同步脉冲提供同步数据。在提供同步数据之后，脉冲沿同步提供同步就绪信号。在一个实施例中，同步脉冲发生在时钟的连续上升沿之间，而响应于时钟的中间下降沿提供同步就绪信号。

2. 发明授权

US07680231B2 Adaptive variable length pulse synchronizer 有权
标题翻译：自适应可变长度脉冲同步器
公开(公告)号：US07680231B2
公开(公告)日：2010-03-16
申请号：US11349874
申请日：2006-02-08
申请人： John E. Angello , Satyavathi Akella , Kiyoshi Kase , May Len
发明人： John E. Angello , Satyavathi Akella , Kiyoshi Kase , May Len
IPC分类号： H04L25/38
CPC分类号： H04L25/38 , H04L7/0008
摘要： An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.
摘要翻译：一种自适应可变长度脉冲同步器，包括状态保持器电路，异步脉冲沿检测电路，数据同步电路和脉冲沿同步电路。状态保持电路检测异步脉冲的前沿。在状态保持电路检测到前沿之后，异步脉冲沿检测电路检测异步脉冲的后沿。在检测到异步脉冲之后，异步脉冲沿检测电路还提供与时钟信号同步的脉冲。数据同步电路锁存异步数据，并响应于同步脉冲提供同步数据。在提供同步数据之后，脉冲沿同步提供同步就绪信号。在一个实施例中，同步脉冲发生在时钟的连续上升沿之间，而响应于时钟的中间下降沿提供同步就绪信号。

3. 发明申请

US20080061846A1 INPUT CIRCUIT FOR RECEIVING A VARIABLE VOLTAGE INPUT SIGNAL AND METHOD 有权
标题翻译：用于接收可变电压输入信号和方法的输入电路
公开(公告)号：US20080061846A1
公开(公告)日：2008-03-13
申请号：US11530181
申请日：2006-09-08
申请人： Kiyoshi Kase , May Len
发明人： Kiyoshi Kase , May Len
IPC分类号： H03B1/00
CPC分类号： H03F3/45192 , H03F3/45632 , H03F2203/45352
摘要： An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.
摘要翻译：输入电压电路包括具有用于接收可变输入电压的控制电极的输入晶体管，具有耦合到形成第一节点的输入晶体管的电流电极的电流电极的电压检测晶体管，以及耦合到第二电流的电流源形成第二节点的电压检测晶体管的电极。输入电压电路还包括可变压降晶体管，其具有耦合到第一节点的第一电流电极，耦合到第二节点的控制电极和耦合到输出节点的第二电流电极，其中电压检测晶体管检测到可变输入电压并向可变压降晶体管提供信号。可变压降晶体管产生与可变输入电压的变化成比例的电压降，以确保输出节点处的输出基本恒定。

4. 发明授权

US06906582B2 Circuit voltage regulation 有权
标题翻译：电路电压调节
公开(公告)号：US06906582B2
公开(公告)日：2005-06-14
申请号：US10652530
申请日：2003-08-29
申请人： Kiyoshi Kase , May Len
发明人： Kiyoshi Kase , May Len
IPC分类号： G05F1/56 , G05F1/10
CPC分类号： G05F1/56
摘要： In a circuit including a number of functional blocks of circuits, each block having a minimum operating voltage, a plurality of sense lines from each of the blocks is used to measure local voltage fluctuation at each block. The power voltage(s) of the overall circuit may be globally regulating in the circuit responsive to such locally sensed voltage fluctuations to prevent the local voltages from dropping below the minimum operating voltage for each block.
摘要翻译：在包括多个功能块电路的电路中，每个块具有最小工作电压，来自每个块的多条感测线用于测量每个块处的局部电压波动。整个电路的电源电压可以响应于这种局部检测的电压波动在电路中进行全局调节，以防止局部电压降低到每个块的最小工作电压以下。

5. 发明申请

US20050046467A1 Circuit voltage regulation 有权
标题翻译：电路电压调节
公开(公告)号：US20050046467A1
公开(公告)日：2005-03-03
申请号：US10652530
申请日：2003-08-29
申请人： Kiyoshi Kase , May Len
发明人： Kiyoshi Kase , May Len
IPC分类号： G05F1/56 , G05F1/10
CPC分类号： G05F1/56
摘要： In a circuit including a number of functional blocks of circuits, each block having a minimum operating voltage, a plurality of sense lines from each of the blocks is used to measure local voltage fluctuations at each block. The power voltage(s) of the overall circuit may be globally regulated in the circuit responsive to such locally sensed voltage fluctuations to prevent the local voltages from dropping below the minimum operating voltage for each block.
摘要翻译：在包括多个电路功能块的电路中，每个块具有最小工作电压，来自每个块的多条感测线用于测量每个块处的局部电压波动。响应于这种局部感测的电压波动，整个电路的电源电压可以在电路中被全局调节，以防止局部电压降低到每个块的最小工作电压以下。

6. 发明申请

US20090160484A1 Input buffer 有权
标题翻译：输入缓冲区
公开(公告)号：US20090160484A1
公开(公告)日：2009-06-25
申请号：US12004617
申请日：2007-12-21
申请人： Kiyoshi Kase , May Len , Dzung T. Tran
发明人： Kiyoshi Kase , May Len , Dzung T. Tran
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.
摘要翻译：用于缓冲输入信号的方法和相应系统包括响应于输入信号低于较低阈值输出第一逻辑值。响应于输入信号上升到较低阈值以上而输出第二逻辑值。此后，维持第二逻辑值，直到输入超过较高阈值，然后低于较高阈值。响应于输入信号低于较高阈值，第一逻辑值被输出并保持在第一逻辑值，直到输入低于低阈值，然后上升到低于下阈值。

7. 发明授权

US07358796B2 Input circuit for receiving a variable voltage input signal and method 有权
标题翻译：用于接收可变电压输入信号和方法的输入电路
公开(公告)号：US07358796B2
公开(公告)日：2008-04-15
申请号：US11530181
申请日：2006-09-08
申请人： Kiyoshi Kase , May Len
发明人： Kiyoshi Kase , May Len
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03F3/45192 , H03F3/45632 , H03F2203/45352
摘要： An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.
摘要翻译：输入电压电路包括具有用于接收可变输入电压的控制电极的输入晶体管，具有耦合到形成第一节点的输入晶体管的电流电极的电流电极的电压检测晶体管，以及耦合到第二电流的电流源形成第二节点的电压检测晶体管的电极。输入电压电路还包括可变压降晶体管，其具有耦合到第一节点的第一电流电极，耦合到第二节点的控制电极和耦合到输出节点的第二电流电极，其中电压检测晶体管检测到可变输入电压并向可变压降晶体管提供信号。可变压降晶体管产生与可变输入电压的变化成比例的电压降，以确保输出节点处的输出基本恒定。

8. 发明申请

US20050146355A1 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US20050146355A1
公开(公告)日：2005-07-07
申请号：US10747748
申请日：2003-12-29
申请人： Kiyoshi Kase , May Len , Dzung Tran
发明人： Kiyoshi Kase , May Len , Dzung Tran
IPC分类号： H03K3/356 , H03K17/10 , H03K19/094
CPC分类号： H03K17/102 , H03K3/356008 , H03K3/356113
摘要： A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.
摘要翻译：具有不同阈值电压的交叉耦合反相器的电平移位器。在上电期间，电平转换器的输出被拉到已知的电压状态。在一些示例中，一个反相器包括附加的N沟道晶体管，其中由于附加晶体管，阈值电压大于另一个反相器的阈值电压。

9. 发明授权

US07479813B2 Low voltage circuit with variable substrate bias 有权
标题翻译：具有可变衬底偏置的低压电路
公开(公告)号：US07479813B2
公开(公告)日：2009-01-20
申请号：US11424132
申请日：2006-06-14
申请人： Kiyoshi Kase , Dzung T. Tran , May Len
发明人： Kiyoshi Kase , Dzung T. Tran , May Len
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： G05F3/205
摘要： In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.
摘要翻译：在一种形式中，电路具有偏置级，其具有用于接收输入信号的输入信号端子。该电路用驱动级修改输入信号以提供补码形式的输出信号。电路的驱动级中的驱动晶体管具有连接到负载的端子和耦合到输入信号端子的控制电极的体积。电路的偏置级中的偏置晶体管具有直接连接到负载的端子和驱动晶体管体的体积。偏置晶体管具有耦合到输入信号端子的控制电极。输入信号偏置驱动晶体管和偏置晶体管的体积，并降低晶体管阈值电压。电路输出阻抗的线性提高，RF干扰降低。还提供较低的电压操作。

10. 发明申请

US20080122520A1 LOW VOLTAGE CIRCUIT WITH VARIABLE SUBSTRATE BIAS 有权
标题翻译：具有可变基板偏置的低电压电路
公开(公告)号：US20080122520A1
公开(公告)日：2008-05-29
申请号：US11424132
申请日：2006-06-14
申请人： Kiyoshi Kase , Dzung T. Tran , May Len
发明人： Kiyoshi Kase , Dzung T. Tran , May Len
IPC分类号： G05F3/02
CPC分类号： G05F3/205
摘要： In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.
摘要翻译：在一种形式中，电路具有偏置级，其具有用于接收输入信号的输入信号端子。该电路用驱动级修改输入信号以提供补码形式的输出信号。电路的驱动级中的驱动晶体管具有连接到负载的端子和耦合到输入信号端子的控制电极的体积。电路的偏置级中的偏置晶体管具有直接连接到负载的端子和驱动晶体管体的体积。偏置晶体管具有耦合到输入信号端子的控制电极。输入信号偏置驱动晶体管和偏置晶体管的体积，并降低晶体管阈值电压。电路输出阻抗的线性提高，RF干扰降低。还提供较低的电压操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式