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1. 发明申请

US20090003105A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090003105A1
公开(公告)日：2009-01-01
申请号：US11768824
申请日：2007-06-26
申请人： Kiyoo ITOH , Riichiro Takemura
发明人： Kiyoo ITOH , Riichiro Takemura
IPC分类号： H01L27/108 , G11C7/12
CPC分类号： H01L27/10897 , G11C11/4091 , G11C11/4097 , G11C2211/4016 , H01L27/0207 , H01L27/108 , H01L27/1203 , H01L27/1207
摘要： A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.
摘要翻译：提供能够以1V以下工作的高速低电压DRAM存储单元和阵列外围电路。 DRAM单元由利用FD-SOI MOST结构的存储单元晶体管和平面电容器组成。由于没有结漏电流，消除了存储电荷的损失，并且可以实现低电压操作。此外，使用FD-SOI MOST的交叉耦合型读出放大器中的栅极和阱连接。通过这种方式，阈值动态地变化，并且可以实现高速感测操作。

2. 发明申请

US20100271864A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100271864A1
公开(公告)日：2010-10-28
申请号：US12768514
申请日：2010-04-27
申请人： Kiyoo ITOH , Riichiro Takemura
发明人： Kiyoo ITOH , Riichiro Takemura
IPC分类号： G11C11/24 , G11C7/00
CPC分类号： H01L27/10897 , G11C11/4091 , G11C11/4097 , G11C2211/4016 , H01L27/0207 , H01L27/108 , H01L27/1203 , H01L27/1207
摘要： A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.
摘要翻译：提供能够以1V以下工作的高速低电压DRAM存储单元和阵列外围电路。 DRAM单元由利用FD-SOI MOST结构的存储单元晶体管和平面电容器组成。由于没有结漏电流，消除了存储电荷的损失，并且可以实现低电压操作。此外，使用FD-SOI MOST的交叉耦合型读出放大器中的栅极和阱连接。通过这种方式，阈值动态地变化，并且可以实现高速感测操作。

3. 发明申请

US20100277996A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100277996A1
公开(公告)日：2010-11-04
申请号：US12028538
申请日：2008-02-08
申请人： Riichiro TAKEMURA , Kiyoo ITOH , Tomonori SEKIGUCHI , Takeshi SAKATA , Katsutaka KIMURA
发明人： Riichiro TAKEMURA , Kiyoo ITOH , Tomonori SEKIGUCHI , Takeshi SAKATA , Katsutaka KIMURA
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.
摘要翻译：一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。使用网状电力线电路提供过驱动的可能性。通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。

4. 发明申请

US20110292709A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110292709A1
公开(公告)日：2011-12-01
申请号：US13117374
申请日：2011-05-27
申请人： Shinichi TAKAYAMA , Akira KOTABE , Kiyoo ITOH , Tomonori SEKIGUCHI
发明人： Shinichi TAKAYAMA , Akira KOTABE , Kiyoo ITOH , Tomonori SEKIGUCHI
IPC分类号： G11C5/06 , G11C7/06
CPC分类号： G11C7/08 , G11C11/4091 , G11C11/4094
摘要： A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.
摘要翻译：半导体器件包括读出放大器电路。读出放大器电路包括执行放大的交叉耦合的第一晶体管和第二晶体管。交叉耦合晶体管的源极分别与第三晶体管和第四晶体管串联连接，并且通过施加到第三和第四晶体管的控制电极的控制电压来控制第三和第四晶体管的电流供应能力。在数据保持期间，保持数据所需的最小子阈值电流根据控制电压流向第三和第四晶体管，并保持位线电位。

5. 发明申请

US20100182076A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20100182076A1
公开(公告)日：2010-07-22
申请号：US12688967
申请日：2010-01-18
申请人： Hiroyuki MIZUNO , Kiyoo ITOH , Masanao YAMAOKA
发明人： Hiroyuki MIZUNO , Kiyoo ITOH , Masanao YAMAOKA
IPC分类号： G05F1/10
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit device achieving an active state in which a high speed operation is performed and an inactive state in which a low leakage state is retained while an internal logical state is retained, and a transition between the two states can be achieved at high speed with low noise and low power. A power control circuit provided between a first power-supply line for providing a first external power-supply voltage and a second power-supply line for providing a second external power-supply voltage includes an output MOSFET. A constant OFF current flows in the MOSFET even if a gate and a source of the output MOSFET are put in the same voltage, and a threshold voltage of the output MOSFET is smaller than that of an internal circuit MOSFET.
摘要翻译：实现进行高速运转的活动状态的半导体集成电路器件和保持内部逻辑状态时保持低泄漏状态的无效状态，并且可以高速地实现两种状态之间的转变噪音低，功耗低。设置在用于提供第一外部电源电压的第一电源线和用于提供第二外部电源电压的第二电源线之间的功率控制电路包括输出MOSFET。即使输出MOSFET的栅极和源极处于相同的电压，并且输出MOSFET的阈值电压小于内部电路MOSFET的阈值电压，恒定的关断电流也流入MOSFET。

6. 发明申请

US20080309369A1 SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM 失效
标题翻译：具有功率降低机制的半导体集成电路
公开(公告)号：US20080309369A1
公开(公告)日：2008-12-18
申请号：US12133969
申请日：2008-06-05
申请人： Takeshi SAKATA , Kiyoo ITOH , Masashi HORIGUCHI
发明人： Takeshi SAKATA , Kiyoo ITOH , Masashi HORIGUCHI
IPC分类号： H03K19/003 , G05F1/10
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.
摘要翻译：包括第一和第二电力线的半导体器件，以及耦合在电力线之间的第一和第二电路块。第一开关元件插入在第一电路块和至少一个电源线之间，并且第二开关元件插入在第二电路块和至少一个电源线之间。第一开关元件被导通以允许第一电路块通过第一和第二电力线接收电力电压，而第二开关元件变得不导通，以防止第二电路块通过第一和第二电力接收电力电压使得流过第二电路的漏电流被抑制。

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