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1. 发明申请

US20100277996A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100277996A1
公开(公告)日：2010-11-04
申请号：US12028538
申请日：2008-02-08
申请人： Riichiro TAKEMURA , Kiyoo ITOH , Tomonori SEKIGUCHI , Takeshi SAKATA , Katsutaka KIMURA
发明人： Riichiro TAKEMURA , Kiyoo ITOH , Tomonori SEKIGUCHI , Takeshi SAKATA , Katsutaka KIMURA
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.
摘要翻译：一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。使用网状电力线电路提供过驱动的可能性。通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。

2. 发明申请

US20120218819A1 NONVOLATILE SEMICONDUCTOR MEMORY 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：US20120218819A1
公开(公告)日：2012-08-30
申请号：US13305988
申请日：2011-11-29
申请人： Masataka KATO , Tetsuo ADACHI , Toshihiro TANAKA , Toshio SASAKI , Hitoshi KUME , Katsutaka KIMURA
发明人： Masataka KATO , Tetsuo ADACHI , Toshihiro TANAKA , Toshio SASAKI , Hitoshi KUME , Katsutaka KIMURA
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.
摘要翻译：公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中的非易失性存储单元。此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

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