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1. 发明申请

US20120218819A1 NONVOLATILE SEMICONDUCTOR MEMORY 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：US20120218819A1
公开(公告)日：2012-08-30
申请号：US13305988
申请日：2011-11-29
申请人： Masataka KATO , Tetsuo ADACHI , Toshihiro TANAKA , Toshio SASAKI , Hitoshi KUME , Katsutaka KIMURA
发明人： Masataka KATO , Tetsuo ADACHI , Toshihiro TANAKA , Toshio SASAKI , Hitoshi KUME , Katsutaka KIMURA
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.
摘要翻译：公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中的非易失性存储单元。此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

2. 发明申请

US20110051515A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20110051515A1
公开(公告)日：2011-03-03
申请号：US12791177
申请日：2010-06-01
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.
摘要翻译：公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中的非易失性存储单元。此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

3. 发明申请

US20070297257A1 Semiconductor memory device capable of canceling out noise development 审中-公开
标题翻译：能够消除噪声发展的半导体存储器件
公开(公告)号：US20070297257A1
公开(公告)日：2007-12-27
申请号：US11889902
申请日：2007-08-17
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.
摘要翻译：动态RAM包含多个动态存储单元，每个动态存储单元包括具有作为选择端子的栅极集合的MOSFET，作为输入/输出端子的一个源极和漏极组，以及连接到电容器的存储节点的另一个源极和漏极以及电容器，分别连接到多个动态存储单元的选择端子的多个字线，分别连接到多个动态存储单元的输入/输出端子的多个互补位线对，以及读出放大器阵列包括多个锁存电路，其分别放大互补位线对之间的电压差，以便从每对输入/输出端子彼此相反的方向延伸。电源线以网格形式提供，包括字驱动器上方的一部分。

4. 发明申请

US20070195596A1 Semiconductor integrated circuit device, production and operation method thereof 有权
标题翻译：半导体集成电路器件，其生产和操作方法
公开(公告)号：US20070195596A1
公开(公告)日：2007-08-23
申请号：US11700085
申请日：2007-01-31
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0425 , G11C16/12 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.
摘要翻译：一种半导体集成器件，具有多个存储单元，每个存储单元包括通过绝缘膜形成在浮置栅极的侧表面上的浮置栅极，控制栅极和辅助栅极。耦合到选择的存储单元的辅助栅极用于产生热电子，并且与其他辅助栅极交替布置，其功能是防止未选择的存储器单元中的写入错误。

5. 发明申请

US20060039218A1 Semiconductor device 失效
公开(公告)号：US20060039218A1
公开(公告)日：2006-02-23
申请号：US11206016
申请日：2005-08-18
申请人： Riichiro Takemura , Kiyoo Itoh , Tomonori Sekiguchi , Takeshi Sakata , Katsutaka Kimura
发明人： Riichiro Takemura , Kiyoo Itoh , Tomonori Sekiguchi , Takeshi Sakata , Katsutaka Kimura
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

6. 发明授权

US06944080B2 Dynamic random access memory(DRAM) capable of canceling out complimentary noise developed in plate electrodes of memory cell capacitors 有权
标题翻译：动态随机存取存储器（DRAM）能够消除在存储单元电容器的平板电极中产生的互补噪声
公开(公告)号：US06944080B2
公开(公告)日：2005-09-13
申请号：US10938794
申请日：2004-09-13
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/02 , G11C7/18 , G11C8/00 , G11C11/34 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring using the common electrodes.
摘要翻译：一种动态RAM，包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到所述多个动态存储单元的输入/输出端的多个互补位线对，并且被放置在与以及根据操作定时信号提供工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。在动态RAM中，与以感测放大器阵列为中心的两侧的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接而通过使用公共电极的布线来确保读出放大器阵列中的电路连接。

7. 发明授权

US06819613B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06819613B2
公开(公告)日：2004-11-16
申请号：US10692811
申请日：2003-10-27
申请人： Riichiro Takemura , Kiyoo Itoh , Tomonori Sekiguchi , Takeshi Sakata , Katsutaka Kimura
发明人： Riichiro Takemura , Kiyoo Itoh , Tomonori Sekiguchi , Takeshi Sakata , Katsutaka Kimura
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.
摘要翻译：一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。使用网状电力线电路提供过驱动的可能性。通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。

8. 发明授权

US06807120B2 Dynamic random access memory (DRAM) capable of canceling out complementary noise developed in plate electrodes of memory cell capacitors 有权
标题翻译：动态随机存取存储器（DRAM）能够消除在存储单元电容器的平板电极中产生的互补噪声
公开(公告)号：US06807120B2
公开(公告)日：2004-10-19
申请号：US10309180
申请日：2002-12-04
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C702
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A semiconductor device includes a first region having first bit lines, first word lines and first memory cells; a second region having second bit lines, second word lines and second memory cells; a third region having sense amplifiers placed between the first region and the second region; a first conductive layer being over the first region; a second conductive layer being over the second region; and a connecting layer, being over the third region, which electrically connects the first conductive layer with the second conductive layer. The sense amplifiers amplify differences in voltage between the first bit lines and the second bit lines. Each of the first memory cells includes a first storage capacitor having an electrode connected to the first conductive layer. Each of the second memory cells includes a second storage capacitor having an electrode connected to the second conductive layer.
摘要翻译：半导体器件包括具有第一位线，第一字线和第一存储器单元的第一区域; 具有第二位线的第二区域，第二字线和第二存储器单元; 具有放置在所述第一区域和所述第二区域之间的读出放大器的第三区域; 在所述第一区域之上的第一导电层; 在所述第二区域上方的第二导电层; 以及连接层，其在第三区域之上，其将第一导电层与第二导电层电连接。感测放大器放大第一位线和第二位线之间的电压差。每个第一存储单元包括具有连接到第一导电层的电极的第一存储电容器。每个第二存储单元包括具有连接到第二导电层的电极的第二存储电容器。

9. 发明授权

US06671198B2 Semiconductor device 有权
公开(公告)号：US06671198B2
公开(公告)日：2003-12-30
申请号：US10354122
申请日：2003-01-30
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C506
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

10. 发明授权

US06636437B2 Programming method of nonvolatile semiconductor memory device 有权
公开(公告)号：US06636437B2
公开(公告)日：2003-10-21
申请号：US10260407
申请日：2002-10-01
申请人： Naoki Kobayashi , Hideaki Kurata , Katsutaka Kimura , Takashi Kobayashi , Shunichi Saeki
发明人： Naoki Kobayashi , Hideaki Kurata , Katsutaka Kimura , Takashi Kobayashi , Shunichi Saeki
IPC分类号： G11C1604
CPC分类号： G11C11/5628
摘要： In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.

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