专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07005686B1 Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time 失效
标题翻译：混合耐压静电放电保护可控硅整流器，增加开启时间
公开(公告)号：US07005686B1
公开(公告)日：2006-02-28
申请号：US11161184
申请日：2005-07-26
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad , Andreas D. Stricker , Min Woo
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad , Andreas D. Stricker , Min Woo
IPC分类号： H01L29/66 , H01L21/33
CPC分类号： H01L27/0262 , H01L29/87
摘要： Disclosed is a method for increasing substrate resistance in a silicon controlled rectifier in order to decrease turn on time so that the silicon controlled rectifier may be used as an effective electrostatic discharge protection device to protect against HBM, MM and CDM discharge events. Additionally, disclosed is an improved SCR structure that is adapted for use as an electrostatic discharge device to protect against human body model events by delivering an electrostatic discharge current directly to a ground rail. The improved SCR structure incorporates various features for increasing substrate resistance and, thereby, for decreasing turn on time. These features include a second n-well that functions as an obstacle to current flow, a narrow current flow channel between co-planar buried n-bands connected to a lower portion of the second n-well, a zero threshold voltage area, and an external resistor electrically connected between the SCR and the ground rail.
摘要翻译：公开了一种用于增加可控硅整流器中的衬底电阻以减少导通时间的方法，使得可控硅整流器可以用作有效的静电放电保护装置，以防止HBM，MM和CDM放电事件。此外，公开了一种改进的SCR结构，其适于用作静电放电装置，以通过将静电放电电流直接递送到接地轨来防止人体模型事件。改进的SCR结构包含用于增加衬底电阻并因此减少导通时间的各种特征。这些特征包括作为电流流动的障碍的第二n阱，连接到第二n阱的下部的共平面埋入n波段之间的窄电流流动通道，零阈值电压区域和外部电阻电连接在SCR和接地导轨之间。

2. 发明申请

US20090258464A1 METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER 审中-公开
标题翻译：使用混合方向技术制造高电压连接场效应晶体管的方法
公开(公告)号：US20090258464A1
公开(公告)日：2009-10-15
申请号：US12099904
申请日：2008-04-09
申请人： Renata Camillo-Castillo , Robert J. Gauthier, JR. , Richard A. Phelps , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Robert J. Gauthier, JR. , Richard A. Phelps , Andreas D. Stricker
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L27/098 , H01L29/045 , H01L29/0649 , H01L29/0843 , H01L29/1066 , H01L29/165 , H01L29/66901
摘要： Methods for manufacturing a high voltage junction field effect transistor. The method includes forming an opening extending from a top surface of a device layer of a hybrid orientation technology (HOT) wafer through the device layer and an insulating layer to expose a portion of a bulk layer, and filling the opening with epitaxial semiconductor material having the crystalline orientation of the bulk layer. The method further includes forming first and second p-n junctions in the epitaxial semiconductor material that are arranged in depth within the epitaxial semiconductor material between the second semiconductor layer and the top surface of the first semiconductor layer.
摘要翻译：制造高压结场效应晶体管的方法。该方法包括从混合定向技术（HOT）晶片的器件层的顶表面延伸通过器件层和绝缘层形成开口以露出本体层的一部分，并且用具有外延半导体材料的开口填充开口，该外延半导体材料具有本体层的晶体取向。该方法还包括在外延半导体材料中形成在第二半导体层和第一半导体层的顶表面之间的外延半导体材料内的深度布置的第一和第二p-n结。

3. 发明申请

US20090256174A1 DEVICE STRUCTURES FOR A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR MANUFACTURED USING A HYBRID ORIENTATION TECHNOLOGY WAFER AND DESIGN STRUCTURES FOR A HIGH VOLTAGE INTEGRATED CIRCUIT 失效
标题翻译：使用混合方向技术制造的高电压场效应晶体管的器件结构和用于高压集成电路的设计结构
公开(公告)号：US20090256174A1
公开(公告)日：2009-10-15
申请号：US12121286
申请日：2008-05-15
申请人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
IPC分类号： H01L29/778
CPC分类号： H01L29/808 , H01L29/0692
摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.
摘要翻译：高压结场效应晶体管的器件结构和高压集成电路的设计结构。使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

4. 发明授权

US08242584B2 Structure and method to create stress trench 有权
标题翻译：构造应力沟的结构和方法
公开(公告)号：US08242584B2
公开(公告)日：2012-08-14
申请号：US12647796
申请日：2009-12-28
申请人： Renata A. Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
发明人： Renata A. Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
IPC分类号： H01L29/06
CPC分类号： H01L29/8086 , H01L21/76283 , H01L29/66901 , H01L29/7846
摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.
摘要翻译：提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。还公开了相关方法。

5. 发明申请

US20120326766A1 Silicon Controlled Rectifier with Stress-Enhanced Adjustable Trigger Voltage 有权
标题翻译：具有应力增强可调触发电压的硅控整流器
公开(公告)号：US20120326766A1
公开(公告)日：2012-12-27
申请号：US13168232
申请日：2011-06-24
申请人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, JR. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, JR. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas D. Stricker
IPC分类号： H03K17/72 , H01L29/74 , G06F17/50 , H01L21/311
CPC分类号： H01L29/7315 , G06F17/5063 , H01L27/0262 , H01L29/66393 , H01L29/7436
摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.
摘要翻译：可控硅整流器的器件结构，制造方法，操作方法和设计结构。该方法包括以足以调节SCR的触发电流的水平对可控硅整流器（SCR）的区域施加机械应力。装置和设计结构包括具有阳极的SCR，阴极，第一区域和与第一区域相反的导电类型的第二区域。 SCR的第一和第二区域设置在SCR的阳极和阴极之间的通电路径中。层相对于第一区域定位在半导体衬底的顶表面上，并且被配置为在SCR的第一区域中产生一个足以调制SCR的触发电流的电平的机械应力。

6. 发明申请

US20110156223A1 STRUCTURE AND METHOD TO CREATE STRESS TRENCH 有权
标题翻译：结构和方法创建应力梯度
公开(公告)号：US20110156223A1
公开(公告)日：2011-06-30
申请号：US12647796
申请日：2009-12-28
申请人： Renata A. Camillo-Castillo , Robert J. Gauthier, JR. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
发明人： Renata A. Camillo-Castillo , Robert J. Gauthier, JR. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/8086 , H01L21/76283 , H01L29/66901 , H01L29/7846
摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.
摘要翻译：提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。还公开了相关方法。

7. 发明授权

US07791105B2 Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit 失效
标题翻译：使用混合取向技术晶圆制造的高压结场效应晶体管的器件结构和用于高压集成电路的设计结构
公开(公告)号：US07791105B2
公开(公告)日：2010-09-07
申请号：US12121286
申请日：2008-05-15
申请人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
IPC分类号： H01L29/778
CPC分类号： H01L29/808 , H01L29/0692
摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.
摘要翻译：高压结场效应晶体管的器件结构和高压集成电路的设计结构。使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

8. 发明申请

US20110309471A1 TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有侧向定义的内部基极到极端基底连接区域的晶体管结构及形成结构的方法
公开(公告)号：US20110309471A1
公开(公告)日：2011-12-22
申请号：US12817249
申请日：2010-06-17
申请人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L29/66242 , H01L29/66287 , H01L29/7378
摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.
摘要翻译：公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度发射极层）进行选择性调整，以优化晶体管性能。

9. 发明授权

US06965133B2 Method of base formation in a BiCMOS process 失效
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US06965133B2
公开(公告)日：2005-11-15
申请号：US10708598
申请日：2004-03-13
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/737 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

10. 发明授权

US06858485B2 Method for creation of a very narrow emitter feature 失效
标题翻译：用于创建非常窄的发射器特征的方法
公开(公告)号：US06858485B2
公开(公告)日：2005-02-22
申请号：US10249780
申请日：2003-05-07
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L21/8238
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面上的掺杂发射极。在收集器上方的本征基底层上形成蚀刻停止介电层。在蚀刻停止介电层和本征基极层上形成导电材料的基底接触层。在基底接触层上形成第二介电层。通过介电层和基底接触层蚀刻宽窗口，停止在蚀刻停止介电层处的窗口的蚀刻。形成一个岛屿或一个半岛，缩小广阔的窗户，在宽阔的窗口内至少留出一个狭窄的窗户。在宽窗口或狭窄的窗户中形成侧壁间隔物。用掺杂多晶硅填充窗口以形成外部发射极。在本征基表面的外部发射极之下形成发射体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式