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1. 发明授权

US08242584B2 Structure and method to create stress trench 有权
标题翻译：构造应力沟的结构和方法
公开(公告)号：US08242584B2
公开(公告)日：2012-08-14
申请号：US12647796
申请日：2009-12-28
申请人： Renata A. Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
发明人： Renata A. Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
IPC分类号： H01L29/06
CPC分类号： H01L29/8086 , H01L21/76283 , H01L29/66901 , H01L29/7846
摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.
摘要翻译：提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。还公开了相关方法。

2. 发明申请

US20090256174A1 DEVICE STRUCTURES FOR A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR MANUFACTURED USING A HYBRID ORIENTATION TECHNOLOGY WAFER AND DESIGN STRUCTURES FOR A HIGH VOLTAGE INTEGRATED CIRCUIT 失效
标题翻译：使用混合方向技术制造的高电压场效应晶体管的器件结构和用于高压集成电路的设计结构
公开(公告)号：US20090256174A1
公开(公告)日：2009-10-15
申请号：US12121286
申请日：2008-05-15
申请人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
IPC分类号： H01L29/778
CPC分类号： H01L29/808 , H01L29/0692
摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.
摘要翻译：高压结场效应晶体管的器件结构和高压集成电路的设计结构。使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

3. 发明授权

US07791105B2 Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit 失效
标题翻译：使用混合取向技术晶圆制造的高压结场效应晶体管的器件结构和用于高压集成电路的设计结构
公开(公告)号：US07791105B2
公开(公告)日：2010-09-07
申请号：US12121286
申请日：2008-05-15
申请人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
IPC分类号： H01L29/778
CPC分类号： H01L29/808 , H01L29/0692
摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.
摘要翻译：高压结场效应晶体管的器件结构和高压集成电路的设计结构。使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

4. 发明授权

US07005686B1 Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time 失效
标题翻译：混合耐压静电放电保护可控硅整流器，增加开启时间
公开(公告)号：US07005686B1
公开(公告)日：2006-02-28
申请号：US11161184
申请日：2005-07-26
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad , Andreas D. Stricker , Min Woo
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad , Andreas D. Stricker , Min Woo
IPC分类号： H01L29/66 , H01L21/33
CPC分类号： H01L27/0262 , H01L29/87
摘要： Disclosed is a method for increasing substrate resistance in a silicon controlled rectifier in order to decrease turn on time so that the silicon controlled rectifier may be used as an effective electrostatic discharge protection device to protect against HBM, MM and CDM discharge events. Additionally, disclosed is an improved SCR structure that is adapted for use as an electrostatic discharge device to protect against human body model events by delivering an electrostatic discharge current directly to a ground rail. The improved SCR structure incorporates various features for increasing substrate resistance and, thereby, for decreasing turn on time. These features include a second n-well that functions as an obstacle to current flow, a narrow current flow channel between co-planar buried n-bands connected to a lower portion of the second n-well, a zero threshold voltage area, and an external resistor electrically connected between the SCR and the ground rail.
摘要翻译：公开了一种用于增加可控硅整流器中的衬底电阻以减少导通时间的方法，使得可控硅整流器可以用作有效的静电放电保护装置，以防止HBM，MM和CDM放电事件。此外，公开了一种改进的SCR结构，其适于用作静电放电装置，以通过将静电放电电流直接递送到接地轨来防止人体模型事件。改进的SCR结构包含用于增加衬底电阻并因此减少导通时间的各种特征。这些特征包括作为电流流动的障碍的第二n阱，连接到第二n阱的下部的共平面埋入n波段之间的窄电流流动通道，零阈值电压区域和外部电阻电连接在SCR和接地导轨之间。

5. 发明授权

US08598660B2 Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage 有权
公开(公告)号：US08598660B2
公开(公告)日：2013-12-03
申请号：US13150612
申请日：2011-06-01
申请人： Renata Camillo-Castillo , Erik Mattias Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Jed Hickory Rankin , Yun Shi
发明人： Renata Camillo-Castillo , Erik Mattias Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Jed Hickory Rankin , Yun Shi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66492 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835 , H01L29/7843
摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

6. 发明授权

US08586423B2 Silicon controlled rectifier with stress-enhanced adjustable trigger voltage 有权
公开(公告)号：US08586423B2
公开(公告)日：2013-11-19
申请号：US13168232
申请日：2011-06-24
申请人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas Stricker
发明人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas Stricker
IPC分类号： H01L21/02
CPC分类号： H01L29/7315 , G06F17/5063 , H01L27/0262 , H01L29/66393 , H01L29/7436
摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

7. 发明授权

US08737028B2 RC-triggered ESD clamp device with feedback for time constant adjustment 有权
标题翻译： RC触发ESD钳位装置，具有时间常数调整反馈
公开(公告)号：US08737028B2
公开(公告)日：2014-05-27
申请号：US13312047
申请日：2011-12-06
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra
IPC分类号： H02H9/04 , G06F17/50
CPC分类号： H02H9/046
摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.
摘要翻译：用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。场效应晶体管与反相器的输出端相连。响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

8. 发明授权

US08692291B2 Passive devices for FinFET integrated circuit technologies 有权
标题翻译： FinFET集成电路技术的无源器件
公开(公告)号：US08692291B2
公开(公告)日：2014-04-08
申请号：US13431456
申请日：2012-03-27
申请人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
发明人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L27/0262 , H01L27/1211
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。形成器件结构，其包括器件区域中的第一导电类型的阱和阱中的第二导电性的掺杂区域。器件区域由绝缘体上半导体衬底的器件层的一部分组成。掺杂区域和阱的第一部分限定了结。阱的第二部分位于器件区域的掺杂区域和外部侧壁之间。可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

9. 发明授权

US08637353B2 Through silicon via repair 失效
标题翻译：通过硅片修复
公开(公告)号：US08637353B2
公开(公告)日：2014-01-28
申请号：US13013378
申请日：2011-01-25
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/82
CPC分类号： H01L22/30 , H01L21/76886 , H01L21/76898 , H01L22/14 , H01L22/20 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , Y10T29/5313 , Y10T29/532 , H01L2924/00
摘要： Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.
摘要翻译：用于改变布线路径的电阻的方法和系统。将布线路径的电阻与目标电阻值进行比较。如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。

10. 发明授权

US08514535B2 Electrostatic discharge device control and structure 失效
标题翻译：静电放电装置的控制和结构
公开(公告)号：US08514535B2
公开(公告)日：2013-08-20
申请号：US12987276
申请日：2011-01-10
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
IPC分类号： H02H3/22
CPC分类号： H01L27/0285
摘要： Structures and methods for electrostatic discharge (ESD) device control in an integrated circuit are provided. An ESD protection structure includes an input/output (I/O) pad, and an ESD field effect transistor (FET) including a drain connected to the I/O pad, a source connected to ground, and a gate. A first control FET includes a drain connected to the I/O pad, a source connected to the gate of the ESD FET, and a gate connected to ground. A second control FET includes a drain connected to the gate of the ESD FET and the source of the first control FET, a source connected to ground, and a gate connected to the I/O pad.
摘要翻译：提供集成电路中静电放电（ESD）器件控制的结构和方法。 ESD保护结构包括输入/输出（I / O）焊盘和包括连接到I / O焊盘的漏极，连接到地的源极和栅极的ESD场效应晶体管（FET）。第一控制FET包括连接到I / O焊盘的漏极，连接到ESD FET的栅极的源极和连接到地的栅极。第二控制FET包括连接到ESD FET的栅极和第一控制FET的源极的漏极，连接到地的源极和连接到I / O焊盘的栅极。

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