专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090085152A1 THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME 失效
标题翻译：三维垂直电子熔断器结构及其制造方法
公开(公告)号：US20090085152A1
公开(公告)日：2009-04-02
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L23/62 , H01L21/44
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译：本文提供三维垂直电子熔丝结构及其制造方法。形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。垂直e熔丝结构包括第一接触层和第二接触层。该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。当施加电流时，导电材料具有增加的电阻。

2. 发明授权

US08232190B2 Three dimensional vertical E-fuse structures and methods of manufacturing the same 失效
标题翻译：三维垂直E熔丝结构及其制造方法
公开(公告)号：US08232190B2
公开(公告)日：2012-07-31
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译：本文提供三维垂直电子熔丝结构及其制造方法。形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。垂直e熔丝结构包括第一接触层和第二接触层。该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。当施加电流时，导电材料具有增加的电阻。

3. 发明申请

US20080303139A1 CHIP-IN-SLOT INTERCONNECT FOR 3D CHIP STACKS 失效
标题翻译：用于3D芯片堆叠的插槽插槽互连
公开(公告)号：US20080303139A1
公开(公告)日：2008-12-11
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

4. 发明授权

US07700410B2 Chip-in-slot interconnect for 3D chip stacks 失效
标题翻译：用于3D芯片堆栈的片上插槽互连
公开(公告)号：US07700410B2
公开(公告)日：2010-04-20
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L21/44
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

5. 发明授权

US06635548B2 Capacitor and method for forming same 失效
公开(公告)号：US06635548B2
公开(公告)日：2003-10-21
申请号：US10046595
申请日：2001-10-26
申请人： Kerry Bernstein , Nicholas Theodore Schmidt , Anthony K. Stamper , Stephen Arthur St. Onge , Steven Howard Voldman
发明人： Kerry Bernstein , Nicholas Theodore Schmidt , Anthony K. Stamper , Stephen Arthur St. Onge , Steven Howard Voldman
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/31053 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of forming an integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the method includes depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are formed in the first insulator layer, and the first insulator layer is etched to form a trench therein between the first and second conductive lines. A first conductive layer is deposited over the first and second conductive lines the said trench. A second insulator layer is deposited over the first conductive layer, and a second conductive layer is deposited over the second insulator layer. Then, a third conductive line is formed and disposed in the trench, the third conductive line overlying the second conductive barrier layer.

6. 发明授权

US06545330B1 On chip alpha-particle detector 有权
公开(公告)号：US06545330B1
公开(公告)日：2003-04-08
申请号：US09614234
申请日：2000-07-12
申请人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
发明人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
IPC分类号： H01L2714
CPC分类号： H01L27/14683 , G01T1/244 , H01L27/14659 , H01L31/115 , H01L31/118
摘要： An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

7. 发明授权

US06452251B1 Damascene metal capacitor 有权
标题翻译：大马士革金属电容器
公开(公告)号：US06452251B1
公开(公告)日：2002-09-17
申请号：US09540737
申请日：2000-03-31
申请人： Kerry Bernstein , Robert M. Geffken , Anthony K. Stamper , Stephen A. St. Onge
发明人： Kerry Bernstein , Robert M. Geffken , Anthony K. Stamper , Stephen A. St. Onge
IPC分类号： H01L2900
CPC分类号： H01L23/5223 , H01L21/76877 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A capacitor (60 and 126) fabricated on a semiconductor chip which has a strap contact (41A, 119A) which interconnects the bottom plate (41B, 111A) of the capacitor into the chip circuitry. In one version, an extension of the material making up the bottom plate of the capacitor forms the strap contact. In another version, the capacitor (185) includes a folding of the bottom plate, dielectric layer and top plate to utilize available space and thus increase its capacitance. Several manufacturing methods allow for integration of fabrication of the various versions of the capacitor into a standard dual or single damascene manufacturing process, including a copper damascene process.
摘要翻译：制造在具有将电容器的底板（41B，111A）互连到芯片电路中的带接触（41A，119A）的半导体芯片上制造的电容器（60和126）。在一个版本中，构成电容器底板的材料的延伸形成带接触。在另一版本中，电容器（185）包括底板，电介质层和顶板的折叠，以利用可用空间并因此增加其电容。几种制造方法允许将各种形式的电容器的制造集成到标准的双重或单个镶嵌制造工艺中，包括铜镶嵌工艺。

8. 发明授权

US06384468B1 Capacitor and method for forming same 失效
标题翻译：电容器及其形成方法
公开(公告)号：US06384468B1
公开(公告)日：2002-05-07
申请号：US09499577
申请日：2000-02-07
申请人： Kerry Bernstein , Nicholas Theodore Schmidt , Anthony K. Stamper , Stephen Arthur St. Onge , Steven Howard Voldman
发明人： Kerry Bernstein , Nicholas Theodore Schmidt , Anthony K. Stamper , Stephen Arthur St. Onge , Steven Howard Voldman
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L21/31053 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the capacitor includes a first insulator layer overlying an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are provided in the first insulator layer and are separated by a trench defined by the first insulator layer and by sidewalls of the first and second conductive lines. A first conductive barrier layer overlies and connects the first and second conductive lines, and a second insulator layer overlies the first conductive barrier layer. A second conductive barrier layer overlies the second insulator layer, and a third conductive line is disposed in the trench and overlies the second conductive barrier layer.
摘要翻译：公开了集成电路互连电平电容器。在示例性实施例中，电容器包括覆盖具有有源器件的半导体衬底的互连级表面上的第一绝缘体层。第一和第二导线设置在第一绝缘体层中，并由第一绝缘体层限定的沟槽和第一和第二导电线的侧壁分开。第一导电阻挡层覆盖并连接第一和第二导电线，并且第二绝缘体层覆盖在第一导电阻挡层上。第二导电阻挡层覆盖在第二绝缘体层上，并且第三导电线设置在沟槽中并覆盖在第二导电阻挡层上。

9. 发明授权

US06645789B2 On chip alpha-particle detector 失效
公开(公告)号：US06645789B2
公开(公告)日：2003-11-11
申请号：US10246136
申请日：2002-09-18
申请人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
发明人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
IPC分类号： H01L2100
CPC分类号： H01L27/14683 , G01T1/244 , H01L27/14659 , H01L31/115 , H01L31/118
摘要： An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

10. 发明授权

US06548338B2 Integrated high-performance decoupling capacitor and heat sink 失效
标题翻译：集成高性能去耦电容和散热片
公开(公告)号：US06548338B2
公开(公告)日：2003-04-15
申请号：US09764504
申请日：2001-01-17
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译：一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式