专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080303139A1 CHIP-IN-SLOT INTERCONNECT FOR 3D CHIP STACKS 失效
标题翻译：用于3D芯片堆叠的插槽插槽互连
公开(公告)号：US20080303139A1
公开(公告)日：2008-12-11
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

2. 发明授权

US07700410B2 Chip-in-slot interconnect for 3D chip stacks 失效
标题翻译：用于3D芯片堆栈的片上插槽互连
公开(公告)号：US07700410B2
公开(公告)日：2010-04-20
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L21/44
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

3. 发明授权

US08881379B2 Method of making heat sink for integrated circuit devices 有权
标题翻译：为集成电路器件制造散热片的方法
公开(公告)号：US08881379B2
公开(公告)日：2014-11-11
申请号：US13460871
申请日：2012-05-01
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
IPC分类号： H05B3/00 , H01C1/084 , H01C7/10
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

4. 发明授权

US08631570B2 Through wafer vias with dishing correction methods 有权
标题翻译：通过具有凹陷校正方法的晶片通孔
公开(公告)号：US08631570B2
公开(公告)日：2014-01-21
申请号：US13369414
申请日：2012-02-09
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10 , H05K3/02 , H05K3/10 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.
摘要翻译：提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

5. 发明授权

US07994895B2 Heat sink for integrated circuit devices 失效
标题翻译：散热器用于集成电路设备
公开(公告)号：US07994895B2
公开(公告)日：2011-08-09
申请号：US11777389
申请日：2007-07-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

6. 发明申请

US20110177670A1 THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 有权
标题翻译：通过硅胶通过光刻对准和注册
公开(公告)号：US20110177670A1
公开(公告)日：2011-07-21
申请号：US12690299
申请日：2010-01-20
申请人： Russell T. Herrin , Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Russell T. Herrin , Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L21/71
CPC分类号： H01L21/76898 , G03F9/7076 , G03F9/708 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.
摘要翻译：一种制造集成电路结构的方法在衬底中形成第一开口并且用保护性衬垫对第一开口进行排列。该方法将材料沉积到第一开口中并在基底上形成保护材料。保护材料包括工艺控制标记，并且包括在第一开口上方并对准第二开口的第二开口。该方法通过保护材料中的第二开口从第一开口移除材料。过程控制标记包括在保护材料内的仅部分延伸穿过保护材料的凹槽，使得在过程控制标记之下的基底的部分不受去除材料的过程的影响。

7. 发明申请

US20110037161A1 ELECTROSTATIC CHUCKING OF AN INSULATOR HANDLE SUBSTRATE 有权
标题翻译：绝缘子手柄底座的静电切割
公开(公告)号：US20110037161A1
公开(公告)日：2011-02-17
申请号：US12540510
申请日：2009-08-13
申请人： Paul S. Andry , Edward C. Cooney, III , Edmund J. Sprogis , Anthony K. Stamper , Cornelia K. Tsang
发明人： Paul S. Andry , Edward C. Cooney, III , Edmund J. Sprogis , Anthony K. Stamper , Cornelia K. Tsang
IPC分类号： H01L23/488 , H01L21/78 , H01L21/50
CPC分类号： H01L24/10 , H01L23/5384 , H01L24/13 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01327 , H01L2924/04953 , H01L2924/12044 , H01L2924/15311 , H01L2924/00 , H01L2924/00014 , H01L2924/049
摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.
摘要翻译：电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。使用粘合剂层将半导体衬底附接到透明手柄衬底。半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。然后可以将半导体中介层结合到封装衬底或半导体芯片。

8. 发明授权

US07052925B2 Method for manufacturing self-compensating resistors within an integrated circuit 有权
标题翻译：在集成电路内制造自补偿电阻的方法
公开(公告)号：US07052925B2
公开(公告)日：2006-05-30
申请号：US10709039
申请日：2004-04-08
申请人： William J. Murphy , Edmund J. Sprogis , Anthony K. Stamper , Erick G. Walton
发明人： William J. Murphy , Edmund J. Sprogis , Anthony K. Stamper , Erick G. Walton
IPC分类号： H01L31/26
CPC分类号： H01L28/20 , H01L27/0802 , Y10T29/49082 , Y10T29/49085
摘要： A method for manufacturing a self-compensating resistor within an integrated circuit is disclosed. The self-compensating resistor includes a first resistor and a second resistor. The first resistor having a first resistance value is initially formed, and then the second resistor having a second resistance value is subsequently formed. The second resistor is connected in series with the first resistor. The second resistance value is less than the first resistance value, but the total resistance value of the first and second resistors lies beyond a desired target resistance range. Finally, an electric current is sent to the second resistor to change the dimension of the second resistor such that the total resistance value of the first and second resistors falls within the desired target resistance range.
摘要翻译：公开了一种在集成电路内制造自补偿电阻器的方法。自补偿电阻器包括第一电阻器和第二电阻器。初始形成具有第一电阻值的第一电阻器，然后形成具有第二电阻值的第二电阻器。第二个电阻与第一个电阻串联。第二电阻值小于第一电阻值，但是第一和第二电阻器的总电阻值超过期望的目标电阻范围。最后，向第二电阻器发送电流以改变第二电阻器的尺寸，使得第一和第二电阻器的总电阻值落在期望的目标电阻范围内。

9. 发明申请

US20120137515A1 THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS 有权
标题翻译：通过具有循环校正方法的WAVER VIAS
公开(公告)号：US20120137515A1
公开(公告)日：2012-06-07
申请号：US13369414
申请日：2012-02-09
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.
摘要翻译：提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

10. 发明授权

US08166651B2 Through wafer vias with dishing correction methods 有权
标题翻译：通过具有凹陷校正方法的晶片通孔
公开(公告)号：US08166651B2
公开(公告)日：2012-05-01
申请号：US12181359
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10 , H05K3/02 , H05K3/10 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.
摘要翻译：一种形成贯穿晶片通孔的方法，包括通过（TWV）形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前，使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触，并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层，所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式