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    • 3. 发明申请
    • DETECTOR FOR ALPHA PARTICLE OR COSMIC RAY
    • ALPHA颗粒或COSMIC RAY的检测器
    • US20050012045A1
    • 2005-01-20
    • US10604416
    • 2003-07-18
    • John FifieldPaul KartschokeWilliam KIaasenStephen KosonockyRandy MannJeffery OppoldNorman Rohrer
    • John FifieldPaul KartschokeWilliam KIaasenStephen KosonockyRandy MannJeffery OppoldNorman Rohrer
    • G01J1/00G11C11/412
    • G11C11/4125
    • A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.
    • 一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。 本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。 冗余修复锁存器在上电时通常写入一次,以记录失败的锁存数据,并且通常不会再次写入。 如果其中一个锁存器由于SER(软错误率(例如α粒子或宇宙射线的击穿))事件而改变状态,则SRAM的冗余锁存器中的修复数据现在将被错误地映射。 检测器电路和方法监视锁存器以发生SER事件,并且响应于此,将修复数据重新加载到冗余修复锁存器。 检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。 在第二实施例中,检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。 检测电路的第二个应用是传统的逻辑电路。
    • 5. 发明申请
    • METHOD OF REDUCING INSTANTANEOUS CURRENT DRAW AND AN INTEGRATED CIRCUIT MADE THEREBY
    • 减少瞬时电流抽取和集成电路的方法
    • US20050086620A1
    • 2005-04-21
    • US10605683
    • 2003-10-17
    • Paul KartschokeNorman Rohrer
    • Paul KartschokeNorman Rohrer
    • G06F9/45G06F17/50
    • G06F17/5045
    • A method (200, 300, 400, 500) utilizing available timing slack in the various timing paths (108) of a synchronous integrated circuit (104) to reduce the overall instantaneous current draw across the circuit. In the method, each timing path is analyzed to determine its late mode margin or its late mode margin and early mode margin. A delay is added to each timing path having a late mode margin greater than zero. In one embodiment, the delay is equal to the corresponding late mode margin. In another embodiment, the delay is equal to the difference between the corresponding late and early mode margins. Each delay effectively shifts the peak current draw for the corresponding timing path within each clock cycle so that the peaks do not occur simultaneously across all timing paths. In other embodiments, the peak overall instantaneous current draw can be further reduced by reducing the delay in some of the delayed timing paths.
    • 一种在同步集成电路(104)的各种定时路径(108)中利用可用的定时松弛的方法(200,300,400,500)来减少整个电路上的总瞬时电流消耗。 在该方法中,分析每个定时路径以确定其延迟模式余量或其延迟模式余量和早期模式余量。 延迟增加到具有大于零的延迟模式余量的每个定时路径。 在一个实施例中,延迟等于相应的延迟模式余量。 在另一个实施例中,延迟等于相应的延迟和早期模式余量之间的差异。 每个延迟有效地移动每个时钟周期内对应的时序路径的峰值电流消耗,使得峰值不会在所有定时路径上同时发生。 在其他实施例中,可以通过减少一些延迟定时路径中的延迟来进一步减小峰值总瞬时电流消耗。
    • 8. 发明申请
    • ERROR DETECTION AND CORRECTION IN SEMICONDUCTOR STRUCTURES
    • 半导体结构中的错误检测和校正
    • US20070241398A1
    • 2007-10-18
    • US11277306
    • 2006-03-23
    • Timothy DaltonMarc FaucherPaul KartschokePeter Sandon
    • Timothy DaltonMarc FaucherPaul KartschokePeter Sandon
    • H01L27/12H01L27/01H01L31/0392
    • H01L25/0657G01R31/318513H01L2225/06513H01L2225/06596H01L2924/0002H01L2924/00
    • A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.
    • 半导体结构及其操作方法。 半导体结构包括第一半导体芯片和第二半导体芯片。 第一半导体芯片位于第二半导体芯片的顶部并结合到第二半导体芯片上。 第一和第二半导体芯片包括第一和第二电节点。 第二半导体芯片还包括第一比较电路。 半导体结构还包括通过将第一半导体芯片的第一电节点电连接到第二半导体芯片的第一比较电路的第一耦合。 第一比较电路能够(i)直接从第二电节点接收输入信号,(ii)通过第一耦合通路间接接收来自第一电节点的输入信号,以及(iii)将第一不匹配信号置于 对来自第一和第二电节点的输入信号的响应是不同的。
    • 9. 发明申请
    • VOLTAGE DROOP DYNAMIC RECOVERY
    • 电压动态动态恢复
    • US20070192636A1
    • 2007-08-16
    • US11276101
    • 2006-02-14
    • Christopher GonzalezPaul KartschokeVinod RamaduraiMathew Ringler
    • Christopher GonzalezPaul KartschokeVinod RamaduraiMathew Ringler
    • G06F1/00
    • G06F1/28
    • Method and systems for dynamically recovering from voltage droops are disclosed. In one embodiment, a microprocessor coupled to a plurality of voltage sensing circuits is provided. The microprocessor includes an instruction sequencing unit and pipeline including a first series of instructions. A central voltage droop detection processor may be coupled to each of the voltage sensing circuits and the microprocessor. Voltage droop is detected using a voltage sensing circuit, after which processing of the microprocessor is interrupted. The pipeline may then be cleared. Subsequently, a second series of instructions including the first series of instructions, and additional instructions are issued. The additional instructions may include stall instructions that cause a delay in processing of the first series of instructions, which prevents re-occurrence of the voltage droop. The interruption and re-issuing also signals the microprocessor that all the data in a particular instruction stream might not be valid and allows recovery.
    • 公开了用于从电压下降动态恢复的方法和系统。 在一个实施例中,提供耦合到多个电压感测电路的微处理器。 微处理器包括指令排序单元和包括第一系列指令的流水线。 中央电压下降检测处理器可以耦合到每个电压感测电路和微处理器。 使用电压检测电路检测电压下降,之后中断微处理器的处理。 然后可以清除管道。 随后,发出包括第一系列指令和附加指令的第二系列指令。 附加指令可以包括导致​​处理第一系列指令的延迟的停止指令,这防止电压下降的再次发生。 中断和重新发出也向微处理器指示特定指令流中的所有数据可能无效并允许恢复。