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1. 发明申请

US20110035714A1 SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS 有权
标题翻译：系统和方法在静态时序分析期间的共同历史缓解
公开(公告)号：US20110035714A1
公开(公告)日：2011-02-10
申请号：US12538229
申请日：2009-08-10
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.
摘要翻译：一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入对当前段的信号具有有界历史，至少一个传播和断言。该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

2. 发明授权

US08108816B2 Device history based delay variation adjustment during static timing analysis 有权
标题翻译：静态时序分析期间基于设备历史的延迟变化调整
公开(公告)号：US08108816B2
公开(公告)日：2012-01-31
申请号：US12484293
申请日：2009-06-15
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.
摘要翻译：一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个基于历史的延迟变异性和时间传播。

3. 发明授权

US08141014B2 System and method for common history pessimism relief during static timing analysis 有权
标题翻译：静态时序分析中共同历史悲观缓解的系统和方法
公开(公告)号：US08141014B2
公开(公告)日：2012-03-20
申请号：US12538229
申请日：2009-08-10
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.
摘要翻译：一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入对当前段的信号具有有界历史，至少一个传播和断言。该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

4. 发明申请

US20100318951A1 SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS 有权
标题翻译：基于静态时序分析的基于设备历史的延迟变化调整系统与方法
公开(公告)号：US20100318951A1
公开(公告)日：2010-12-16
申请号：US12484293
申请日：2009-06-15
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.
摘要翻译：一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个基于历史的延迟变异性和时间传播。

5. 发明授权

US08707233B2 Systems and methods for correlated parameters in statistical static timing analysis 失效
标题翻译：统计静态时序分析中相关参数的系统和方法
公开(公告)号：US08707233B2
公开(公告)日：2014-04-22
申请号：US13190083
申请日：2011-07-25
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081
摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.
摘要翻译：提供了适应SSTA相关参数的系统和方法。该方法包括确定至少两个参数之间的相关性。该方法还包括基于至少两个参数之间的相关性计算新参数或新参数集。该方法还包括执行SSTA，使得新参数或新参数集传播到SSTA中。该方法还包括使用至少两个参数之间的相关性并使用处理器来投影松弛。

6. 发明申请

US20130031523A1 SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS 失效
公开(公告)号：US20130031523A1
公开(公告)日：2013-01-31
申请号：US13190083
申请日：2011-07-25
申请人： Eric A. FOREMAN , Peter A. HABITZ , David J. HATHAWAY , Jeffrey G. Hemmett , Natesan VENKATESWARAN , Chandramouli VISWESWARIAH , Vladimir ZOLOTOV
发明人： Eric A. FOREMAN , Peter A. HABITZ , David J. HATHAWAY , Jeffrey G. Hemmett , Natesan VENKATESWARAN , Chandramouli VISWESWARIAH , Vladimir ZOLOTOV
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F17/5081
摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

7. 发明申请

US20120124534A1 System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times 失效
标题翻译：在断定到达时间之间相关性的情况下执行静态时序分析的系统和方法
公开(公告)号：US20120124534A1
公开(公告)日：2012-05-17
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译：一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

8. 发明授权

US08056038B2 Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip 有权
标题翻译：用于有效地检查和重新启动集成电路芯片的静态时序分析的方法
公开(公告)号：US08056038B2
公开(公告)日：2011-11-08
申请号：US12354360
申请日：2009-01-15
申请人： Kerim Kalafala , Hemlata Gupta , David J. Hathaway , Jeffrey G. Hemmett
发明人： Kerim Kalafala , Hemlata Gupta , David J. Hathaway , Jeffrey G. Hemmett
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.
摘要翻译：在边界到达时间，转数，所需到达时间或负载与检查点运行不同的环境中加载检查点定时的方法。为一个或多个分层模块生成的定时检查点文件，在此期间为每个输入分配唯一的相位标签。独特相位标签的关联允许随后的重新启动分析以有效地调整与重启定时环境相关的检查点定时。在重新启动运行中，读取一个或多个这样的检查点文件，在此期间，执行到达的初始传播，所需到达和转换时间，然后基于调整的到达时间和所需的到达时间进行本地重新更新。最后，如果更新了多个分级模块，则基于松弛变化阈值执行定时值的全局重新计算，以便确定是否引入了任何新的定时故障。

9. 发明申请

US20100180244A1 Method For Efficiently Checkpointing And Restarting Static Timing Analysis Of An Integrated Circuit Chip 有权
标题翻译：有效地检查和重新启动集成电路芯片的静态时序分析的方法
公开(公告)号：US20100180244A1
公开(公告)日：2010-07-15
申请号：US12354360
申请日：2009-01-15
申请人： Kerim Kalafala , Hemlata Gupta , David J. Hathaway , Jeffrey G. Hemmett
发明人： Kerim Kalafala , Hemlata Gupta , David J. Hathaway , Jeffrey G. Hemmett
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.
摘要翻译：在边界到达时间，转数，所需到达时间或负载与检查点运行不同的环境中加载检查点定时的方法。为一个或多个分层模块生成的定时检查点文件，在此期间为每个输入分配唯一的相位标签。独特相位标签的关联允许随后的重新启动分析以有效地调整与重启定时环境相关的检查点定时。在重新启动运行中，读取一个或多个这样的检查点文件，在此期间，执行到达的初始传播，所需到达和转换时间，然后基于调整的到达时间和所需的到达时间进行本地重新更新。最后，如果更新了多个分级模块，则基于松弛变化阈值执行定时值的全局重新计算，以便确定是否引入了任何新的定时故障。

10. 发明授权

US08689158B2 System and method for performing static timing analysis in the presence of correlations between asserted arrival times 失效
标题翻译：在断言到达时间之间存在相关性的情况下执行静态时序分析的系统和方法
公开(公告)号：US08689158B2
公开(公告)日：2014-04-01
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译：一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

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